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Freescale Semiconductor SC140 Rule G.P.1, Example 7-16 Vles Extension Words Exceed Two

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Static Programming Rules

Rule G.P.1

Up to two extension words can be grouped in a VLES. This means:

•A three-word instruction can only be grouped in a VLES with one-word instructions.

Example 7-16 VLES Extension Words Exceed Two

[	; 1st extension word
bmset #$ab34,d3.l	; 1st extension word
move.l #$f0d0,vba	; not allowed - 2nd & 3rd extension word
]

•A two-word instruction can only be grouped in a VLES with one other two-word instruction and/or one-word instructions.

Example 7-17 Two-Word Instructions Exceed Two

[	; 1st extension word
move.f #$1234,d0	; 1st extension word
extract #8,#16,d0,d2	; 2nd extension word
extractu #8,#24,d0,d3	; not allowed - 3rd extension word
zxt.b d0,d0
]

The second and third words of an instruction are called “extension words.” An extension word can occur in the following cases:

•Some immediate values

•Some absolute addresses or offsets

•Bit mask instructions listed in Table A-16: Prefix Instructions on page A-18

•INSERT or EXTRACT/U instructions

•Integer double precision instructions such as IMACxx, IMACxxxx, IMPYxx, IMPYxxxx and

IMPY.W

7-12	SC140 DSP Core Reference Manual

Image 262

Freescale Semiconductor SC140 specifications Rule G.P.1, Example 7-16 Vles Extension Words Exceed Two

Contents

SC140 DSP Core Reference ManualSC140 DSP Core Reference Manual Table of Contents SC140 DSP Core Reference Manual Control Registers SC140 DSP Core Reference Manual Program Control Instruction Set Accelerator Plug-In Programming Rules SC140 DSP Core Instruction Set Appendix aStarCore Registry Appendix BXii List of Figures Xiv List of Tables Xvi SC140 DSP Core Reference Manual Xvii Xviii List of Examples SC140 DSP Core Reference Manual SC140 DSP Core Reference Manual Xxi Xxii About This Book Abbreviations Abbreviations used in this manual are listed belowAbbreviation Description ISR Revision History Revision Date DescriptionChapter Introduction Target MarketsArchitectural Differentiation Core Architecture Features Typical System-On-Chip Configuration System expansion area Variable Length Execution Set Vles Software ModelSoC DSP expansion area SC140 platformCore Architecture Features Chapter Core Architecture Architecture OverviewBlock Diagram of the SC140 Core Data Arithmetic Logic Unit DaluMultiply-Accumulate MAC Unit Address Generation Unit AGUData Register File Bit-Field Unit BFUStack Pointer Registers Bit Mask Unit BMUInstruction Set Accelerator Plug-in Isap Interface Program Sequencer Unit PseqEnhanced On-Chip Emulator EOnCE Memory InterfaceDalu Dalu ArchitectureDalu Programming Model Limit EXTData Registers D0-D15 Read from Data Registers Write to Data RegistersOperand Type Dn.e Dn.h Dn.l Operand Type Data Width Bits Data Registers Access WidthDalu Arithmetic Instructions MAC Instruction DescriptionDIV NEG Data Shifter/Limiter Dalu Logical Instructions BFUCalculating the Ln Bit ScalingLimiting Scaling ExampleLimiting with the Moves Instructions Scaling Mode Bits Defining the Ln bit CalculationLn Bit Calculation Limiting Example Scaling and Arithmetic Saturation Mode InteractionsSelected Special Six Other Dalu Instructions Mode 10. Scaling and Limiting InteractionsData Representation Dalu Arithmetic and Rounding11. Saturation and Rounding Interactions Data Formats Signed Fractional12. Two’s Complement Word Representations Signed IntegerSigned Fractional Signed Integer Unsigned Integer Unsigned Arithmetic MultiplicationDivision Unsigned MultiplicationRounding Modes 13. Rounding Position in Relation to Scaling ModeScaling Mode High Portion Low Portion Unsigned ComparisonConvergent Rounding No Scaling 2.6.2 Two’s Complement Rounding Two’s Complement Rounding No Scaling Arithmetic Saturation Mode 14. Arithmetic Saturation ExampleMulti-Precision Arithmetic Support Fractional Multi-Precision ArithmeticFractional Double-Precision Multiplication Integer Multi-Precision Arithmetic Fractional Mixed-Precision Multiplication10. Signed Integer Double-Precision Multiplication Viterbi Decoding Support 11. Unsigned Integer Double-Precision MultiplicationAddress Generation Unit AGU ArchitectureArithmetic AddressUnit AAU Address Generation Unit AGU Programming Model 13. AGU Programming ModelAddress Registers R0-R15 Stack Pointer Registers NSP, ESPModifier Registers M0-M3 Offset Registers N0-N3Base Address Registers B0-B7 Shadow Stack Pointer Registers17. Address Modifier AM Bits Modifier Control Register MctlAddress Modifier Modes Register Direct Modes Addressing ModesAddress Register Indirect Modes Address Generation Unit PC Relative Mode Special Addressing Modes Memory Access Width Memory Access Misalignment19. Memory Address Alignment Access Type Aligned AddressAddressing Modes Summary 20. Addressing Modes SummaryPC Relative Address Register IndirectSpecial Modulo Addressing Mode Linear Addressing ModeReverse-carry Addressing Mode Address Modifier Modes15. Modulo Addressing Example 21. Modulo Register Values for Modulo Addressing Mode Multiple Wrap-Around Modulo Addressing ModeModifier Mj Address Calculation Arithmetic Arithmetic Instructions on Address Registers 23. AGU Arithmetic InstructionsBit Mask Instructions Bit Mask Test and Set Semaphore Support Instruction 24. AGU Bit Mask Instructions BMUExample of Normal Usage of the Semaphoring Mechanism Move InstructionsSemaphore Hardware Implementation Label BMTSET.W #mask,R0 JT label25. AGU Move Instructions MOVE.W16. Integer Move Instructions 17. Fractional Move Instructions Memory Interface 18. Bit Allocation in MOVE.L D0.eD1.e1 SC140 Endian Support 1.1 SC140 Bus StructureMemory Organization 20. Basic Connection between SC140 Core and Memory26. Data Representation in Memory Data MovesRepresentation Type Value 22. Data Transfer in Big and Little Endian Modes Multi-Register Moves Address DataMulti-Register Transfer in Big and Little Endian Modes Instruction Word Transfers 25. Instruction Moves in Big and Little Endian Modes Memory Access Behavior in Big/Little Endian Modes Example MOVE.F D0, R0 Example MOVE.L D0.ED1.E, A0Example MOVE.2L D0D1, R0 Example MOVE.2F D0D1, R0Example VSL.4F D2D6D1D3, R0 + N0 Example VSL.4W D2D6D1D3, R0 + N0D6 = Example VSL.2W D1D3, R0 + N0Example BMSET.W #$1234, A0 Example Push D0Example Push D0 Push D1 Data =31. Control Instructions in Big and Little Endian Modes Instruction Register Operands Big Little EndianCore Control Registers Status Register SRDescribes the various SR bits Name Description SettingsStatus Register Description I2-I0 Interrupt Mask Bits Reflect ExceptionsException Mode Bit Selects Overflow Exception Enable BitDisable Interrupts Bit When this bit ReservedScaling Mode Bit Equation ModeS1-S0 Scaling Mode Bits Specify Rounding Mode Bit Selects the typeName Description Settings Arithmetic Saturation Mode Selects Exception and Mode Register EMR Exception and Mode Register EMRDescribes the EMR fields EMR DescriptionIlst Illegal Execution Set Indicates whether anBmclr #$fffb,EMR.L PLL and Clock RegistersClearing EMR Bits Example 3-1. Clearing an EMR BitEmulation and Debug EOnCE Debugging SystemOverview of the Combined Jtag and EOnCE Interface Jtag Interface Signal DescriptionsSignal Name Signal Description Cascading Multiple SC140 EOnCE Modules in a SoCJtag Scan Paths Jtag InstructionsLoadgpr TAP Controller State Machine Jtag Scan Paths Select-DR Scan Path Select-IR Scan PathActivating the EOnCE Through the Jtag Port Enabling the EOnCE ModuleDebugrequest and Enableeonce Commands Reading/Writing EOnCE Registers Through JtagReading and Writing EOnCE Registers Via Jtag EOnCE register write operation through Jtag EOnCE register read capture operation through JtagMain Capabilities of the EOnCE Module EOnCE SignalsEOnCE Signals Jtag Signals Core InterfaceEOnCE Dedicated Instructions Debug StateExecuting an Instruction while in Debug State Debug ExceptionSoftware Downloading Software Downloading EOnCE Event Types EOnCE EventsEvent type Occurs when EOnCE Event and Action Summary EOnCE ActionsEvent and Action Summary Event typeEOnCE Module Internal Architecture EOnCE Enabling and Power ConsiderationsEOnCE Controller Address Monitor and Control Register Command RegisterTransmit Register Update Signal from the TAP Controller Address Control Decoder Logic Receive RegisterEvent Counter Shows a block diagram of the event counter Event Counter Register SetEvent Detection Unit EDU XDBxx Data Buses EE5..0Address Buses EventD Event0 Event1 Event2 Event5 Count eventAddress Event Detection Channel Edca EEiEdca Register Set EventD Data Event Detection Channel EdcdEvent External Event 6,7 Count Event Edcd register set is shown belowEvent Selector ES Optional External Event Detection Address ChannelsEvent0..Event5 External Event6, Event7 EventD Count event EE40 ES block diagram is shown in FigureTrace Unit 10. Event Selector Register SetEOnCE Module Internal Architecture Change of Flow Change of Flow and Interrupt TracingTrace Buffer TB Off-Core Reading the Trace Buffer Tbbuff Writing to the Trace BufferTrace Unit Programming Model EOnCE Register Addressing 11. Trace Buffer Register Set12. EOnCE Register Addressing Offsets 12 displays the EOnCE register addressing offsetsOffset EDCA4REFA Reading or Writing EOnCE Registers Using Core Software Real-Time Jtag AccessGeneral EOnCE Register Issues Real-Time Data TransferEOnCE Register Addressing EOnCE Controller Registers EOnCE Command Register ECRRead/Write Command Specifies 13 describes the ECR fields16 displays the bit configuration of the ESR EOnCE Status Register ESR14. ESR Description 14 describes the ESR fieldsName Description Section DREE3 15. Emcr Description EOnCE Monitor and Control Register Emcr15 describes the Emcr fields Name Description ReservedDebugerst EOnCE Receive Register Ercv EOnCE Transmit Register EtrsmtDetection by the Event Detection Channels EE SignalsEE Signals as Outputs Detecting Entry into Debug StateEE Signals as Inputs EE Signals Control Register Eectrl16. Eectrl Description EeddefEE2DEF 17. Length Control Bits Core Command Register CorecmdLength control bits are described in -17, below Length Control Bits DescriptionPC of Last Execution Set Pclast PC of the Exception Execution Set PcexcpPC of the Next Execution Set Pcnext PC Breakpoint Detection Register PcdetectEvent Counter Registers Event Counter Control Register Ecntctrl18. Ecntctrl Description Extended Mode of Operation Bit18 describes the Ecntctrl fields Reserved for TestEvent Counter Value Register Ecntval Event Counter Enable Used toEvents to be Counted Determines EC Signals Extension Counter Value Register EcntextEdca Control Registers EDCAiCTRL Event Detection Unit EDU Channels and RegistersAddress Event Detection Channel Edca 19 describes the EDCAiCTRL fieldsEvent Detection Channel EDCAi Comparators Selection Used toComparator B Condition Selection Access Type Selection These bitsComparator a Condition Selection Edca Reference Value Registers a and B EDCAiREFA, EDCAiREFB Edca Mask Register EDCAiMASK20 describes the Edcdctrl fields Data Event Detection Channel EdcdEdcd Control Register Edcdctrl 20. Edcdctrl DescriptionAccess Width Selection AWSAccess Type Selection The ATS bit Comparator Condition SelectionEdcd Reference Value Register Edcdref Event Selector ES RegistersEvent Selector Control Register Eselctrl Edcd Mask Register EdcdmaskEselctrl fields are described in Table 21. Eselctrl Description24 displays the bit configuration of Eseldm Event Selector Mask Debug State Register EseldmEvent Selector Mask Enable Trace Register Eseletb Event Selector Mask Debug Exception Register EseldiTrace Unit Registers Event Selector Mask Disable Trace Register EseldtbTrace Buffer Control Register Tbctrl Trace mode This mode is usefull only with the Tcount mode22. Allowed tracing mode combinations Upon a trace event, trace the counter value Ecntval23. Tbctrl Description Trace Buffer Counter ModeTbctrl fields are described in the following table Trace Buffer Extension CounterTrace Mark Instruction Mode Trace Loops Mode Enables tracingTrace Buffer Enable Mode Enables Trace Issue of Execution Sets EnableTrace Buffer Write Pointer Register Tbwr Trace Buffer Read Pointer Register TbrdTrace Buffer Register Tbbuff Trace Unit Registers Chapter Program Control PipelineInstruction Pipeline Stages Illustrates the five instruction pipeline stagesInstruction Cycle Operation Pipeline ExamplePipeline Stages Overview Pipeline Stage DescriptionInstruction Dispatch Instruction Pre-Fetch and FetchAddress Generation Execution Instruction GroupingExample 5-1. Four SC140 Instructions in an Execution Set Grouping Types Instruction Grouping MethodsSerial Grouping Prefix GroupingPrefix Types Two-Word PrefixFor example Conditional ExecutionOne-Word Low Register Prefix Prefix InstructionsAssembly Syntax Meaning Prefix Selection AlgorithmLow Register Prefix Selection Algorithm Instruction Reordering Within an Execution Set Example 5-4. Conditional Vles Having Two Subgroups Example 5-5. Set of 2 Two-word Instructions Requiring a NOPInstruction Timing Sequential Instruction Timing Instruction Categories Timing SummaryBit Mask Instruction Timing Dalu Instruction TimingMove Instruction Timing Compare Shift TestChange-Of-Flow Instruction Timing Example 5-6. Delayed Change-of-Flow and Its Delay SlotNon-Loop Change-of-Flow Instructions Direct, PC-Relative, and Conditional COF Loop Change-Of-Flow InstructionsDelayed COF COF Execution CyclesNumber of Cycles Needed by Change-of-Flow Instructions Example 5-7 shows a case when a stall cycle is addedHighest cycle count of instructions grouped with Call Example 5-7. Subroutine Call TimingMemory Access Timing Memory Access Examples MOVE.L Example 5-8. Parallel Execution of Two Move InstructionsImplicit Push/Pop Memory Timing Memory Stall ConditionsLoop Programming Model Hardware LoopsLoop Start Address Registers SAn Loop Counter Registers LCn Loop Notation and EncodingStatus Register SR Loop Flag Bits Loop Type Loop Initiation and ExecutionLpmarka and Lpmarkb Bits in Short and Long Loops Location FunctionalityLoop Nesting Loop Iteration and Termination10. Loop Control Instructions Loop Control Instructions10 lists the loop instructions Instruction OperationExample 5-12. Long Loop Example 5-13. Long Loop DisassemblyExample 5-14. Short Loop, Two Execution Sets Example 5-15. Short Loop, One Execution Set Following is an example of a nested loopExample 5-16. Nested Loop Loop Timing Stack Support1 SC140 Single Stack Memory Use 2 SC140 Dual Stack Memory Use Shows the stack structure12. Even and Odd Registers Stack Support Instructions11. Stack Push/Pop Instructions Even Register De File Odd Register Do File13. Stack Memory Map Addressing Mode DescriptionShadow Stack Pointer Registers 14. Stack Move InstructionsFast Return from Subroutines Working Mode EXP bit Active SP Normal Working ModeException Working Mode Working ModesTypical Working Mode Usage Scenarios Dual-stack RtosFrom Normal to Exception mode Working Mode TransitionsFrom Exception to Normal mode Single-stack RtosWorking Modes Processing State Change Instructions Processing States16. Processing State Change Instructions 10. Core State Diagram Processing State Transitions17. Processing State Transitions Reset Processing StateExecution State Processing State Transitions DescriptionWait Processing State Stop Processing State 18. Exit Wait Processing State due to an Interrupt or NMIException Processing SC140 11. Core-PIC InterfaceVector Base Address Register Interrupt Vector AddressProgramming Exception Routine Addresses 19. Exception Vector Address Table Return From Exception InstructionsException Address Priority Type Description Offset Highest Internal Exceptions Maskable InterruptsNon-Maskable Interrupts NMI Interrupt Priority LevelIllegal Instruction Illegal ExceptionIllegal Execution Set Trap Exception Exception Interface to the PipelineDalu Overflow Debug Exception20. Exception Pipeline Exception Mode ExecutionException Timing Example 5-17. Basic Exception TimingException Processing 12 provides a flow chart for Example 21. Pipeline Example Instruction Set Accelerator Plug-In IntroductionData Memory Isap SC140 Schematic ConnectionSingle Isap SC140CoreCore to Multiple Isap Connection Schematic Multiple IsapIsap Encoding Fields Isap Memory AccessIsap instructions and instruction encoding Binary Encoding Words BitsISAP-core register transfers Example 6-1. Isap memory accessTo understand this, look at the following lines of code Example 6-2. ISAP-Core register transfers Immediate Data Transfer to Isap registersFollowing line of code Example 6-3. ISAP-Core register transfersWorking with One Isap Core Assembly Syntax with an IsapIdentification of Isap instructions Vles that uses an implicit Isap ID stringOne Isap in a Single-Line Vles Working with Multiple ISAPsOne Isap in a Multi-Line Vles Multiple ISAPs in a Multi-Line Vles An Example of the Definition Flexibility of an IsapExample 6-5. Multiple Isap coding Example 6-6. Conditional Execution Example Example 6-7. Conditional Execution ExampleProgramming Rules Isap Functions that Interact With the CoreGrouping rules for explicit Isap instructions Rules for implicit AGU instructionsSequencing rules for T bit update D.2, D.3Programming Rules Vles Sequencing Semantics Vles Grouping SemanticsVles Grouping Semantics Programming Rule Notation SC140 Pipeline ExposureGrouping Rules Sequencing Rules Register Read/WriteMOVE-like Instructions Status Bit UpdatesInstruction Words Register AliasingAGU Arithmetic Instructions Delayed COF InstructionsDelay Slot Change-Of-Flow DestinationsHardware Loops Enabled LoopStatic Programming Rules Hardware Loop DetectionRule G.G.2 General Grouping RulesRule G.G.1 Rule G.G.3Example 7-6 Duplicate Address Pointer Register Destinations Rule G.G.4Example 7-5 Duplicate PC Destinations Example 7-7 Duplicate Stack Pointer DestinationsExample 7-9 Duplicate SR/EMR Register Destinations Rule G.G.4 ExceptionsExample 7-8 Duplicate Register Destinations Example 7-10 Duplicate Status Bit DestinationsFollowing rules only apply to prefix-grouped Vles Prefix Grouping RulesRule G.G.5 Example 7-15. Dalu Register Use Exceeds Four TimesExample 7-16 Vles Extension Words Exceed Two Rule G.P.1Example 7-17 Two-Word Instructions Exceed Two Rule G.P.5 Rule G.P.3Rule G.P.4 Example 7-18. Vles Has Mutually Exclusive InstructionsExample 7-20. Data Source Use of Nn and Mn Registers Rule G.P.6Rule G.P.7 Example 7-21. IFc Having Two SubgroupsRule G.P.9 Rule G.P.8Example 7-24. Isap instructions in same IFc group Rule A.1 AGU RulesExample 7-25. Mctl Write to R0-R7 Use Rule A.3 Rule A.2Example 7-26. Rn, Nn, Mn Write to AGU Use Example 7-27. Rn or Nn Write to MOVE-like Use Rule A.4Example 7-28. LCn Write to MOVE-like Use Example 7-30. Instructions in a Delay Slot Delayed COF RulesExample 7-29. Nmid Update to EMR Read Rule A.7Rule D.2 Example 7-31. Instructions in a Rted Delay SlotExample RTE/D with SR Updates Rule D.3Rule D.5a Rule D.4Rule D.5 Rule D.6Rule D.9 Status Bit RulesRule D.8 Rule T.1Rule T.2.c Rule T.2.aRule T.2.b Rule SR.2Static Programming Rules Example 7-43. SR Write to SR Status Bit Use Rule SR.3 Example 7-44. SR Write to SR Status Bit UpdateRule SR.4 Example 7-46. Dovf Update grouped with Move-like SR updates Example 7-45. Dovf Update to SR Read or WriteRule SR.4a Rule L.N.1 Loop Nesting RulesRule SR.7 DI and EI DOENn and DOENSHnExample 7-49. Nested Loops with Ordered Index Rule L.N.2Rule L.N.3 Example 7-50. Nested DOENn/DOENSHn InstructionsExample 7-52. Loopend between Doen and Loopend Example 7-53. Changing a loop typeRule L.L.2 Loop LA RulesRule L.L.1 Example 7-54. Instructions at the End of Long LoopsLA of a short loop cannot be at LA-1 of a long loop Rule L.L.3Rule L.L.4 Example 7-56. Instructions in Short LoopsRule L.L.6 Loop Sequencing RulesRule L.L.5 Rule L.D.1Rule L.D.6 Rule L.D.3Rule L.D.5 Example 7-60. LCn Write at the Start of Short Loop nRule L.D.8 Rule L.D.7Rule L.D.9 Rule L.C.2 Loop COF RulesRule L.C.1 Rule L.C.3Bc or Jc instruction is not allowed at LA-3 of a long loop Rule L.C.5Example 7-68. Bc/Jc at LA-3 of a Long Loop Rule L.C.7 Example 7-69. Loop COF Destination in the Same LoopExample 7-70. Loop COF at End of Nested Long Loops Rule L.C.9Rule L.C.10 Example 7-71. Subroutine Call to End of LoopsRule L.C.12 General Looping RulesRule L.C.11 Rule L.G.3Rule L.G.5 Dynamic Programming RulesAGU Dynamic Rules Rule A.2aRule A.6 Memory Access RulesRule A.5 Rule D.7Rule J.4 RAS RulesLoop Rules Rule L.N.6Cycle-Based COF Rules Example 7-83. A.2 from a Delay Slot to a COF DestinationRule Detection Across COF Boundaries Example 7-82. SR.2 Across a COF BoundaryVLES-Based COF Rules Rule SR.2a Example 7-85. EMR access at the start of an exceptionRule Detection Across Exception Boundaries Rule SR.4bRule A.1a Example 7-86. Mctl Write to R0-R7 UseRule J.1 COF destination cannot be a delay slotProgramming Guidelines Rule J.2Source Code Practices Rules Not Detected Across COF BoundariesGood Programming Practices Rule J.5Binary Code Practices Lpmark Instruction Type Lpmark RulesSoftware Development Practices General Grouping Rules Static Programming RulesDynamic Programming Rules Prefix Grouping RulesLoop Nesting Rules Loop LA RulesLpmark Rule L.L.5 Lpmark Rule L.L.2Lpmark Rule L.L.3 Example 7-93. Active LCn Write at the End of Long LoopsLpmark Rule L.D.2 + L.D.3 Loop Sequencing RulesLpmark Rule L.L.6 Lpmark Rule L.D.6COF instructions are not allowed at LPB of a long loop Loop COF RulesLpmark Rule L.C.2 Example 7-97. Active LCn Read at the Start of a LoopExample 7-98. COF Instructions at LPB of a Long Loop Lpmark Rule L.C.3 + L.C.5Example 7-99. Bc/Jc at the Start of a Loop Example 7-100. Loop COF at End of Nested Long Loops Lpmark Rule L.C.9Lpmark Rule L.C.10 Example 7-101. Subroutine Call to End of LoopsGeneral Looping Rules Lpmark Programming GuidelinesRule Detection Across Exception Boundaries NOP Definition Example 7-104. COF Destination to Loop Delay SlotsLpmark Rule L.C.1 Grouping Examples Is encoded asIs assembler mapped to the IFT prefix and encoded as Is assembler mapped to the IFF prefix and encoded asIs encoded ignoring the NOP subgroup as NOP Definition Appendix a SC140 DSP Core Instruction Set Table A-1. Instruction Conventions ConventionsConvention Definition Operator Description Table A-2. Operations SyntaxTable A-3. Register Abbreviations Abbreviation Register NameBrackets as address indicators Brackets as Isap indicatorsTable A-4. Assembler Syntax Table A-6. Addressing Mode Notation for the ea Operand Addressing Mode NotationTable A-5. Addressing Mode Notation for the EA Operand Addressing Mode Definition Notation in Instruction FieldEncoding Notation Data Representation in Memory for the ExamplesDefinition for the field is Prefix Word Encoding Aaa Instruction Formats and OpcodesInstruction Fields CccIf true, all the set Example, 2-w prefix + 2 grouped instruction words, aaa =If true D0, D2, A0, if false D1, D3, A1 Prefix Words Cycles TypeHigh data register is used for the op3 field E3 is set Last, or to last-1 ExampleFirst execution set of the loop High data register is used for the op1 field E2 is setDSP Core Instruction Set Instruction Types Instruction Sub-typesTable A-7. Dalu Arithmetic Instructions MAC Table A-8. Dalu Logical Instructions BFU Table A-9. AGU Arithmetic Instructions Table A-10. AGU Move Instructions Table A-11. AGU Stack Support InstructionsTable A-12. AGU Bit-Mask Instructions BMU Table A-13. AGU Non-Loop Change-of-Flow InstructionsTable A-15. AGU Program Control Instructions Table A-16. Prefix InstructionsInstructions InstInstruction Definition Layout ABS Single Source/Destination Data Register InstructionDc + Dd + C → Dd ADCAdd Long With Carry Dalu ADC Dc,DdDc,Dd Data Register Pairs Register/Memory Address BeforeOperation Assembler Syntax ADDAdd Dalu Add d0,d1,d2Add d1,d0,d2 Da,Da Data Register Pairs Da,Db#u5 Add Two 16-Bit Values Dalu ADD2Add2 d0,d1 JJJ Single Source Data RegisterAdda #u5,Rx AddaAdd AGU Adda #s16,rx,RnAdda r0,r1 Address RegisterAGU Source/Destination Register Rrrr AGU Source Register#s16 Addl1a r0,r1 ADDL1A Add With One-Bit Arithmetic Shift Left ADDL1ASource Operand AGU Rx1 + Rx → RxADDL1A rx,Rx Rx2 + Rx → Rx ADDL2A Add With Two-Bit Arithmetic Shift Left ADDL2AAddl2a r0,r1 ADDL2A rx,RxADDL2A rx,Rx Carry Bit Dalu ADDNC.WAdd Without Changing ADDNC.W Addnc.w #$ca3e,d1,d2Instruction Words Cycles Type Adr d3,d4 ADRAdd and Round Dalu RndDa + Dn → DnADR Da,Dn #u16$0000,Da,Dn Bitwise and Dalu#0u16,Da,Dn Da,Dn#$0ff2e,d2,d1 D2,d1#$ff2e0000,d2,d1 #u16$0000 #0u16#u16 #u16 DR.H → DR.H #$a70e,d1.h#u16 DR.L → DR.L #u16,DR.LData/Address Register Cycles Type OpcodeAND.W #u16,a16 AND.W #u16,RnAND.W #u16,SP-u5 AND.W #u16,SP+s16And.w #$54a1,r7 A16 S16Da 1→ Dn ASLAsl d0,d1 ASL Da,DnASL Da,Dn Rx2 → Rx ASL2AAsl2a r0 ASL2A RxRx1 → Rx AslaAsla r0 Asla RxAsll #u5,Dn AsllMultiple-Bit Arithmetic Shift Left Dalu Asll Da,DnAsll d0,d1 Asll Aslw d0,d1 AslwWord Arithmetic Shift Left 16 Bits Dalu Aslw Da16 → DnAslw Da,Dn Da1 → Dn ASRAsr d5,d3 ASR Da,DnRegister/Memory Address Before After Asra r2 AsraAsra Rx Asrr Multiple-Bit Arithmetic Shift Right DaluAsrr #$3,d5 Asrr d3,d5#u5 Asrw d5,d0 Asrw Da,DnAsrw Da,Dn BF lbl If T==0, then PC + displacement → PCBranch If False AGU BF labelDisplacement label Instruction Words Cycles1 Type OpcodeBFD lbl BFD Branch If False Using a Delay Slot AGU OperationBFD BFD labelLabel Displacement ~C1.Li → C1.Li Bmchg~C1.Hi → C1.Hi i denotes bits=1 in #u16 ~DR.Hi → DR.HiClears the Ln bit in the destination data register Bmchg #$f0f0,d1.hControl Registers Iiiiiiiiiiiiiiii 16-bit unsigned immediate data BMCHG.W Bit-Masked Change aBmchg.w #$661f,$800c BMCHG.W #u16,SP-u5Bit signed SP address offset Bmclr #u16,C1.L Bmclr Bit-Masked Clear a 16-Bit Operand BMU Bmclr OperationBmclr #u16,C1.H Bmclr #u16,DR.HBmclr #$b646,d7.l #u16 Bit-Masked Clear a BMCLR.WBit Operand in Memory BMU Operation Assembler Syntax BMCLR.W #u16,SP-u5 Bmset #u16,DR.H Bmset #u16,C1.HBmset #u16,C1.L Bmset #u16,DR.LBmset #$2436,d1.l BMSET.W Bit Operand in Memory BMURegister/Memory Address Before Immediate Bmset.w #$f111,$800c$800C Bmtset #u16,DR.H BmtsetBmtset #$111f,d1.l Bmtset #u16,DR.LBmtset #$4238,d4.l BMTSET.W Bit-Masked Test and Set a BMTSET.WBmtset.w #$4328,$c BMTSET.W #u16,SP-u5 Bmtstc Bmtstc #$8a59,d7.h$0$0024A60000 $00E40000 BMTSTC.W #u16,SP+s16 BMTSTC.WBMTSTC.W #u16,SP-u5 BMTSTC.W #u16,RnBmtstc.w #$8A59,r0 BMTSTC.W #u16,SP-u5 Bmtsts #u16,DR.H BmtstsBmtsts #u16,C1.L Bmtsts #u16,DR.LBmtsts #$24a6,d7.h BMTSTS.W #u16,SP+s16 BMTSTS.WBMTSTS.W #u16,SP-u5 BMTSTS.W #u16,RnBmtsts.w #$0428,r0 BMTSTS.W #u16,SP-u5 Branch AGU PC + displacement → PCBRA BRA labelAAAAAAAAAA0 Brad label BradSource Code Comments $0000 000A $0000 000E Break label PC + displacement → PCBreak → LFnEncoding is the displacement with bit Status and Conditions Changed by Instruction None Example BSRBranch to Subroutine AGU Bsr labelBSR Next* PC → SP SR → SP + 4 SP + 8 → SP PC + displacement → PC, next* PC→RASBsrd label Bsrd label BT lbl If T==1, then PC + displacement → PCBranch If True AGU BT labelRegister/Memory Address Before BT After BTD lbl BTD Branch If True Using a Delay Slot AGU OperationBTD BTD label$0035 $0000 $0006 $002A $001A $0016 Clb d3,d7 CLBCount Leading Bits Dalu CLB Da,DnCLB Da,Dn Clr d1 CLRClear a Data Register Dalu → DnDestination Data Register Source Data RegisterCmpeq d2,d3 CmpeqCompare for Equal Dalu If Da == Dn, then 1→ T, else 0 → T118 Cmpeq.w #$5,d3 CMPEQ.WCMPEQ.W Compare for Equal Dalu CMPEQ.W #u5,DnCMPEQ.W If rx == Rx, then 1 → T, else 0 → T Cmpeqa Compare for Equal AGU Cmpeqa OperationCmpeqa r1,r2 Cmpeqa rx,RxCmpeqa rx,Rx Cmpgt d2,d3 CmpgtCompare for Greater Than Dalu Dn Da → T124 CMPGT.W #u5,Dn CMPGT.WCmpgt.w #$8002,d2 CMPGT.W #s16,DnCMPGT.W #u5,Dn Cmpgta r2,r3 CmpgtaCompare for Greater Than AGU Cmpgta Rx rx → TCmpgta rx,Rx Cmphi d1,d0 CmphiUnsigned Compare for Higher Dalu Cmphi Cmphi Da,Dn130 Cmphia r0,r1 CmphiaUnsigned Compare for Higher AGU Cmphia Cmphia rx,RxCmphia rx,Rx Label ContContinue to the Next Loop Iteration AGU LabelCycles1 Type Opcode Contd Contd labelCycles1 Type Debug Enter Debug Mode AGUDebug Signal a Debug Event AGU Debugev DebugevDeca r0 DecaDecrement a Register AGU Rx 1 → RxBit unsigned immediate data = 1, set by the assembler Dn 1 → Dn if Dn==0, then 1→ T, else 0 → T Deceq d7Deceq Dn 142 Rx 1 → Rx if Rx==0, then 1 → T, else 0 → T Deceqa Rx Deceqa Decrement and Set T If Equal Zero DeceqaDeceqa r0 Deceqa RxDn 1 → Dn Dn≥0 → T DecgeExample decge Decge DnSC140 DSP Core Reference Manual 145 Rx 1 → Rx Rx ≥ 0 → T DecgeaDecgea r4 Decgea RxDecgea Rx → DI Determines execution working modeSR19 Set disable interrupt bit SR18Page If Dn39 ⊕ Da39 = DIVDivide Iteration Dalu Then 2 * Dn + C + Da & $FF Ffff 0000 → DnDiv d2,d1 DIV Da,Dn Dn16 + Dc.H * Dd.H → Dn DmacssDmacss d2,d3,d5 Dc signed, Dd signedDmacss Dc,Dd,Dn 1 1 Accumulate With Right Shifted Data Register Dalu Dmacsu Multiply Signed By Unsigned and DmacsuDmacsu d2,d3,d5 156 DOENn #u6 Do Enable Long Loop AGUDoen2 d0 DOENn #u16Loop Identifier #u6DOENSHn #u6 Do Enable Short Loop AGU DOENSHnDoensh2 d0 DOENSHn #u16$00E4 $A0E4 PC + displacement → SAn Setup Long Loop DOSETUPnDosetup1 label DOSETUPn labelEncoding is the displacement with SR19 Clears disable interrupt bit → DI164 Eor d4,d5 EORBitwise Exclusive or Dalu Da ⊕ Dn → DnEOR Da,Dn EOR #u16,DR.L Eor #$5,d5.lEOR #u16,DR.H EOR #u16,DR.L EOR #u16,DR.H EOR.W Bitwise Exclusive or onEor.w #$aaaa,r0 Extract #$c,#$e,d2,d4 ExtractExtract Extract Signed Bit Field Dalu Extract #U6,#u6,Db,DnJjj Single Source/Destination Data Register Extractu #$c,#$e,d2,d4 ExtractuExtractu Extract Unsigned Bit Field Extractu #U6,#u6,Db,DnExtractu #U6,#u6,Da,Dn Iaddnc.w #$a002,d2 IADDNC.W #s16,DnElse treat as NOP If T == Then execute group/subgroup Conditionally Execute a Group or Subgroup Prefix IFcIf T == Then execute group/subgroup Else treat as NOP Execute group/subgroup unconditionallyIft move.w #$ffff,d0 Ccc Conditional execution of the entire execution setIllegal Illegal Dn ± Da.L * Db.L → Dn ImacImac d4,d5,d6 Imac ±Da,Db,DnImac -d4,d5,d6 Accumulation Notation182 Dn + Da.L * Db.H → Dn Imaclhuu Da,Db,DnImaclhuu Da,Db,Dn Unsigned By Signed Dalu Operation Assembler Syntax ImacusInteger Multiply Accumulate Imacus d3,d4,d0$0002 x -64 $FFC0 -128 $FF80 +0 $0000 -128 $FF80 Da.L * Db.L → Dn ImpyInteger Multiply Dalu Impy Da,Db,DnD1,D1 D3,D3 D5,D5 D7,D7 #s16 * Dn.L → Dn Impy.w #$fffe,d3IMPY.W #s16,Dn +16 Impyhluu d4,d3,d0 ImpyhluuInteger Multiply Upper Impyhluu Da.H * Db.L → DnImpyhluu Da,Db,Dn Impysu Da,Db,Dn ImpysuImpysu d3,d5,d1 Register Bit Name Description AddressImpysu Da,Db,Dn Impyuu d5,d3,d1 ImpyuuImpyuu Da,Db,Dn 196 Inc d0 INCINC Increment a Data Register By One Dalu Operation INC DnInc d15 Dn + $0000010000 → Dn Inc.f d15INC.F Dn INC.F Dn Inca r0 IncaIncrement Register AGU Rx + 1 → RxInca Rx Insert #12,#22,d6,d7 InsertInsert Bit Field Dalu Insert #U6,#u6,Db,DnInsert #U6,#u6,Db,Dn JF label Jump If False AGUJF lbl JF RnBit absolute long address JFD label JFDJFD Rn $00E0 $00 0000 $0000 $00 0000 002A $00 0000 001A Jmp label JMPJump AGU JMP labelJMP label Example jmpd lbl Jump Using a Delay Slot AGUJmpd Jmpd labelAaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAAA Jsr r6 JSRJump to Subroutine AGU JSR labelAbsolute long address Jsrd label Example jsrd r6Next* PC → RAS Rn → PC Jsrd RnJsrd label JT label Jump If True AGUJt r0 JT RnJT label Example jtd r0 Jump If True Using Delay Slot AGUJTD JTD labelJTD label LCn 1 → LCn Else next PC → PC → LFn If LCn Then SAn → PC LPMARKx End-of-Loop Mark Prefix LPMARKx OperationIf LCn Then SAn → PC LCn 1 → LCn Else next PC → PC → LFn → SLFLFn Status and Conditions that Affect Lpmark ExecutionTable A-17. Combinations of LPMARKx Use LCn DescriptionInsertion of lpmarkb by assembler Status and Conditions Changed by Lpmark ExecutionPrefix Formats and Opcodes Instruction Disassembled Instruction CommentsLsll d4,d2 LsllMultiple-Bit Bitwise Shift Left Dalu Lsll Da,Dn$00E4 $0$FF 8765 Lsr d4 LSRBitwise Shift Right One Bit Dalu Dn1 → Dn 0 → Dn39Lsra r2 LsraBitwise Shift Right By One Bit AGU Rx1 → Rx 0 → Rx31Lsrr Da,Dn LsrrMultiple-Bit Bitwise Shift Right Dalu Lsrr #u5,DnLsrr d4,d2 Before AfterBit unsigned immediate data Lsrw d4,d2 LsrwWord Bitwise Shift Right Dalu Lsrw Da,DnLsrw Da,Dn Mac d4,d5,d6 MACSigned Fractional Multiply-Accumulate Dalu MAC #s16,Da,DnMac #$1000,d5,d6 SC140 DSP Core Reference Manual 235 RndDn ± Da.H * Db.H → Dn MacrMacr d4,d5,d6 Macr ±Da,Db,Dn000 0000 0000 1000 $0008 Instruction Formats and Opcodes 238 Dn + Dc.H * Dd.L → Dn MacsuMacsu d0,d1,d4 Macsu Dc,Dd,Dn111 1111 1111 1111 $FFFF Instruction Formats and Opcodes Dn + Dc.L * Dd.H → Dn MacusMacus Dc,Dd,Dn Macus Dc,Dd,Dn Unsigned By Unsigned Dalu Operation Assembler Syntax MacuuFractional Multiply-Accumulate Macuu d2,d3,d1Macuu Dc,Dd,Dn Push the PC into the Trace Buffer AGU Mark MarkPC → trace buffer Max d0,d4 MAXTransfer Maximum Signed Value Dalu If Dg Dh, then Dg → DhIf Dg.H Dh.H, then Dg.H → Dh.H MAX2Max2 d0,d4 If Dg.L Dh.L, then Dg.L → Dh.L00 D0,D4 01 D1,D5 10 D2,D6 11 D3,D7 248 Else 1 → VFn MAX2VITIf Da.L Db.L, then 0 → VFn, Da.L → Db.L MAX2VIT Da,DbMax2vit d4,d2 Maxm d2,d6 Maxm Transfer Maximum Absolute Value Dalu Maxm OperationMaxm Dg,Dh 00 D0,D4 01 D1,D5 10 D2,D6 11 D3,D7 252 Min d1,d5 MINTransfer Minimum Signed Value Dalu MIN Dg,DhMemory to a Register Pair AGU MOVE.2FMove Two Fractional Words from MOVE.2F DescriptionDaDb Data Register Pairs MOVE.2F EA,DaDbDa,Db ↔ EA MOVE.2LMove.2l d0d1,r0 MOVE.2L DaDb,EA MOVE.2L EA,DaDbRead/Write Notation EA ↔ DaDb MOVE.2WMove.2w d0d1,r0 MOVE.2W EA,DaDb MOVE.2W DaDb,EA$FF Ffff AF44 Memory to a Register Quad AGU MOVE.4FMove Four Fractional Words from MOVE.4F EA → DaDbDcDdMove.4f r0,d0d1d2d3 DaDbDcDd Data Register QuadEA ↔ DaDbDcDd MOVE.4WMOVE.4W EA,DaDbDcDd MOVE.4W DaDbDcDd,EA Move.4w d0d1d2d3,r0 MOVE.B Byte Move AGUMOVE.B SP+s15,DR Move.b d3,r7+$3MOVE.B DR,ea MOVE.B DR,SP+s15MOVE.B a16,DR A32 S15Move Fractional Word MOVE.FTo/from Memory AGU Operation Assembler Syntax MOVE.F SP+s15,Db Move.f $54,d10MOVE.F Db,ea MOVE.F #s16,Db MOVE.F a16,Db SC140 DSP Core Reference Manual 271 MOVE.L Move Long Word AGUCccc General Registers#s32 #u32MOVE.L SP+s15,De.E MOVE.L Da.EDb.E,SP+s15MOVE.L a32,De.E Move.l d0.ed1.e,$1224MOVE.L SP+s15,Do.E MOVE.L Da.EDb.E,a32Data Register Da.EDb.E ff Data Register Extension Pair278 Move Long AGU MOVE.L Rn+u3,DR MOVE.L DR,Rn+u3 MOVE.L a32,DR MOVE.L DR,a32MOVE.L a16,C4 MOVE.L C4,a16 MOVE.L Rn+s15,DR MOVE.L DR,Rn+s15Move.l d0,r0 MOVE.L SP+s15,C4 MOVE.L C4,SP+s15MOVE.L EA,DR MOVE.L DR,EA Rrr Address Register Read/Write NotationUnsigned 3-bit offset MOVE.W #s16,a16 MOVE.W #s7,DRMOVE.W #s16,C4 MOVE.W #s16,SP-u5Move.w #$0050,r7 MOVE.W #s7,DR MOVE.W #s16,C4 #s7 Sa16MOVE.W a32,DR MOVE.W DR,a32 MOVE.WMove Integer Word AGU MOVE.W a16,C4 MOVE.W C4,a16MOVE.W Rn+Rr,DR MOVE.W DR,Rn+Rr MOVE.W Rn+u3,DR MOVE.W DR,Rn+u3MOVE.W Rn+s15,DR MOVE.W DR,Rn+s15 MOVE.W Rn,C3 MOVE.W C3,RnMove.w d1,r7+4 MOVE.W a32,DR MOVE.W DR,a32 Write Sss0 Movet Rq,Rn MOVEc Conditional Address Register Move AGU MOVEc OperationMovet r0,r1 Movef Rq,RnQqq Address Register DaDb → EA MOVES.2F Move Two Fractional Words to MOVES.2FMOVES.2F DaDb,EA $7FFF $7EAC DaDbDcDd → EA Moves.4f d0d1d2d3,r0MOVES.4F DaDbDcDd,EA $7FFF MOVES.F Move Fractional Word toMoves.f d0,r0 MOVES.F Db,a16 304 Memory With Scaling and Saturation AGU Operation MOVES.LMove Long to Moves.l d0,r0MOVES.L Db,EA Move Unsigned Byte from MOVEU.BMemory AGU Operation Assembler Syntax Moveu.b $0053,d10 MOVEU.B a16,DR 310 #u32 → Db MOVEU.LMoveu.l #$fffffff8,d3 MOVEU.L #u32,Db31IIIIIIIIIIIIIIII16 #u16 → Db150 Moveu.w #$2345,d10.l#u16 → Db3116 MOVEU.W #u16,Db.H#u16 Iiiiiiiiiiiiiiii Bit unsigned immediate dataMove Unsigned Word from MOVEU.WMemory to a Register AGU Operation Moveu.w r7+2,d10 MOVEU.W a16,C4 318 Da.H * Db.H → Dn MPYMpy d4,d5,d6 MPY Da,Db,DnMpy d6,d6,d7 SC140 DSP Core Reference Manual 321 RndDa.H * Db.H → Dn MpyrMpyr d4,d5,d6 Mpyr Da,Db,Dn$0000 Register/Memory Address Before After L6D6324 Dc.H * Dd.L → Dn MpysuMpysu d4,d5,d6 Mpysu Dc,Dd,Dn326 Dc.L * Dd.H → Dn MpyusMpyus Dc,Dd,Dn 328 Dc.L * Dd.L → Dn MpyuuMpyuu d4,d5,d6 Mpyuu Dc,Dd,Dn330 Neg d3 NEGNegate Dalu NEG DnNEG Dn No operation NOPNo Operation Prefix NopNot d4,d5 NotBitwise Complement Dalu ~Da → DnSC140 DSP Core Reference Manual 335 Not D0.L Binary Inversion of a 16-Bit Operand BMU~DR.L → DR.L Not DR.L Binary Inversion of a 16-Bit Operand NOT.WMemory BMU Operation Assembler Syntax Not.w r1 Da Dn → Dn Bitwise Inclusive or DaluExample or d3,d0 Or Da,DnSC140 DSP Core Reference Manual 341 #u16 DR.H → DR.H Or #$0f0a,d0.l#u16 DR.L → DR.L Or #u16,DR.LOr #u16,DR.L Or #u16,DR.H OR.W #u16,SP+s16 OR.W #u16,RnOR.W #u16,SP-u5 OR.W #u16,a16Or.w #$f01a,r1 OR.W #u16,Rn346 POP De SP 8 → De SP 8 → SPSP 4 → Do SP 8 → SP POP DoPop d3 Eeeee Extension Pairs, Even Registers, and Loop Start RegistersNSP 8 → De NSP 8 → ΝSP NSP 4 → Do NSP 8 → ΝSPPopn De Popn d6.ed7.ePopn Do 352 Push De De → SP SP + 8 → SPDo → SP + 4 SP + 8 → SP Push DoPush d0.ed1.e SC140 DSP Core Reference Manual 355 Pushn De De → NSP NSP + 8 → ΝSPDo → NSP + 4 NSP + 8 → ΝSP Pushn DoPushn d0.ed1.e Pushn De Pushn Do RndDa → Dn RNDRound Dalu RND Da,DnRnd d1,d5 Rnd d2,d1RND Da,Dn Dn39 → C → Dn0 Rol d5Dn3801 → Dn391 ROL DnROL Dn → Dn39 Dn0 → C Ror d15Dn39-11 → Dn38-0 ROR DnROR Dn SP 8 → PC RTESP 4 → SR SP 8 → SP → Nmid Rte Instruction Words Cycles1 TypeRted Example rted TrapRts RTSReturn From Subroutine AGU If RAS valid, then RAS → PCRTS Rtsd RtsdRtsd Cleared Restore PC from Stack AGURtstk Register Address Bit Name Description EMR3Example rtstk SP 8 → PC RtstkdSP 8 → SP Example rtstkd If Da $007FFFFFFF then $007FFF0000 → Dn SAT.FSat.f d2,d3 SAT.F Da,DnSAT.F Da,Dn Sat.l d6 SAT.LSAT.L Dn SC140 DSP Core Reference Manual 381 Db Dc C → Dd SBCSubtract With Borrow Dalu SBC Dc,DdSBC Dc,Dd Sbr d3,d0 SBRSubtract And Round Dalu RndDn Da → Dn0010 1010 1110 0111 0000 0000 1000$2AE7 Skipls label If LCn ≤ Then PC + displacement → PC Skipls label → LFnSkipls Skipls labelSkipls label Stop Stop Instruction Processing AGU Operation StopEnter the stop processing state Sub d1,d0,d2 SUBSubtract Dalu SUB #u5,DnSub d0,d1,d2 SC140 DSP Core Reference Manual 391 Subtract Two 16-Bit Values Dalu SUB2Sub2 d0,d1 SUB2 Da,Dn Suba r1,r0 SubaSubtract AGU Suba #u5,RxSuba Subl d0,d1 SublShift Left and Subtract Dalu Dn Da → Dn$0$FF Ffff Fffe Dn #s16 → Dn SUBNC.WSubnc.w #$15,d0 SUBNC.W #s16,DnSUBNC.W #s16,Dn Sxt.b d3,d0 Sign-Extension DaluSxt.w d3,d2 Sxt.l d3 Sxta.b r3,r1 Sign-Extension AGUSxta.w r3 SXTA.B Tfr d15,d14 TFRTransfer Data Register to Data Register Dalu Tfr d7,d6TFR Da,Dn Rx → Rx TfraTfra r0,r1 Tfra rx,RxSC140 DSP Core Reference Manual 407 Else ESP → Rn If Srexp = Then Rn → NSP To/from a Register AGUIf Srexp = Then NSP → Rn Else Rn → ESPTfra r0,osp If T=0, then Da → Dn Tfrt d14,d15If T=1, then Da → Dn Tfrt Da, DnTfrt Trap Execute a Software Exception AGU Trap Operation TRAPnTrap Tsteq d1 TsteqTest for Equal to Zero Dalu If Dn == 0, then 1 → T, else 0 → TTsteqa.l r1 TSTEQA.x Test for Equal to Zero AGU TSTEQA.x OperationTsteqa.w r4 TSTEQA.W RxTSTEQA.W TSTEQA.L Tstge d4 TstgeTest for Greater Than Or Equal to Zero Dalu If Dn = 0, then 1 → T, else 0 → TIf Rx ≥ 0, then 1 → T, else 0 → T Tstgea.l r7TESTGEA.L Rx TSTGEA.L Rx If Dn 0, then 1 → T, else 0 → Τ Tstgt Test for Greater Than Zero Dalu Tstgt OperationTstgt d6 Tstgt DnIf Rx 0, then 1 → T, else 0 → Τ Tstgta Test for Greater Than Zero AGU Tstgta OperationTstgta r2 Tstgta RxVSL Word Big Endian ModeLittle Endian Mode Viterbi Shift Left Move AGUVSL.2W D1D3,Rn+N0 VSL.4W D2D6D1D3,Rn+N0VSL.4F D2D6D1D3,Rn+N0 VSL.2F D1D3,Rn+N0After Little Endian Vsl.2w d1d3,r0+n0After Big Endian VSL.4W State Enters the low-power standby Wait processingWait ResponseWait Zxt.b d2,d5 Zero Extension DaluZxt.w d3,d6 Zxt.l d0 Zxta.b r3,n2 Zero Extension AGUZxta.w r4 ZXTA.B ZXTA.x 432 Using the StarCore Registry Appendix B StarCore RegistryHex Bits Instruction Cores Example Table B-1. Scid AssignmentsSet Version SoC / platform Index Ecnten Eeddef Eselctrl 4-26ESELDI 4-26ESELDM 4-26ESELDTB 4-26 Eseletb MOVES.F A-299 MOVES.L A-301 MOVEU.B A-307 Macsu A-239 Macus A-241 Macuu A-243 Mpysu A-325 Mpyus A-327 Mpyuu A-329 Rtstk A-374 Index Index SC140 DSP Core Reference Manual