Intel PXA255 manuals
Home Audio > Speaker System
When we buy new device such as Intel PXA255 we often through away most of the documentation but the warranty.
Very often issues with Intel PXA255 begin only after the warranty period ends and you may want to find how to repair it or just do some service work.
Even oftener it is hard to remember what does each function in Speaker System Intel PXA255 is responsible for and what options to choose for expected result.
Fortunately you can find all manuals for Speaker System on our side using links below.
600 pages 5.16 Mb
2 ii Intel PXA255 Processor Developers Manual3 Contents25 Introduction 11.1 Intel XScale Microarchitecture Features 1.2 System Integration Features26 1.2.1 Memory Controller1.2.2 Clocks and Power Controllers 1.2.3 Universal Serial Bus (USB) Client 27 1.2.4 DMA Controller (DMAC)1.2.5 LCD Controller 1.2.6 AC97 Controller 1.2.7 Inter-IC Sound (I2S) Controller 1.2.8 Multimedia Card (MMC) Controller 1.2.9 Fast Infrared (FIR) Communication Port 28 1.2.10 Synchronous Serial Protocol Controller (SSPC)1.2.11 Inter-Integrated Circuit (I2C) Bus Interface Unit 1.2.12 GPIO 1.2.13 UARTs1.2.13.1 Full Function UART (FFUART) 1.2.13.2 Bluetooth UART (BTUART) 1.2.13.3 Standard UART (STUART) 1.2.13.4 Hardware UART (HWUART) 29 1.2.14 Real-Time Clock (RTC)1.2.15 OS Timers 1.2.16 Pulse-Width Modulator (PWM) 1.2.17 Interrupt Control 1.2.18 Network Synchronous Serial Protocol Port 31 System Architecture 263 Clocks and Power Manager 3105 System Integration Unit 4 4.1 General-Purpose I/O4.1.1 GPIO Operation 106 4.1.2 GPIO Alternate Functions110 4.1.3 GPIO Register Definitions Intel PXA255 Processor Developers Manual 4-7 111 4.1.3.1 GPIO Pin-Level Registers (GPLR0, GPLR1, GPLR2)This is read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Table 4-2. GPIO Register Definitions (Sheet 2 of 2) Table 4-3. GPLR0 Bit Definitions 4-8 Intel PXA255 Processor Developers Manual This is read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. 112 4.1.3.2 GPIO Pin Direction Registers (GPDR0, GPDR1, GPDR2)Table 4-4. GPLR1 Bit Definitions Table 4-5. GPLR2 Bit Definitions Intel PXA255 Processor Developers Manual 4-9 113 Table 4-6. GPDR0 Bit Definitions Table 4-7. GPDR1 Bit Definitions Table 4-8. GPDR2 Bit Definitions 4-10 Intel PXA255 Processor Developers Manual 114 Table 4-10. GPSR1 Bit Definitions Intel PXA255 Processor Developers Manual 4-11 115 Table 4-11. GPSR2 Bit Definitions Table 4-12. GPCR0 Bit Definitions Table 4-13. GPCR1 Bit Definitions Intel PXA255 Processor Developers Manual 4-13 117 Table 4-15. GRER0 Bit Definitions Table 4-16. GRER1 Bit Definitions Table 4-17. GRER2 Bit Definitions 4-14 Intel PXA255 Processor Developers Manual 118 Table 4-18. GFER0 Bit Definitions Table 4-19. GFER1 Bit Definitions Table 4-20. GFER2 Bit Definitions Intel PXA255 Processor Developers Manual 4-15 119 4.1.3.5 GPIO Edge Detect Status Register (GEDR0, GEDR1, GEDR2)Table 4-22. GEDR1 Bit Definitions 120 4.1.3.6 GPIO Alternate Function Register (GAFR0_L, GAFR0_U, GAFR1_L, GAFR1_U, GAFR2_L, GAFR2_U) 123 4.1.3.7 Example Procedure for Configuring the Alternate Function Registers 124 4.2 Interrupt Controller132 4.3 Real-Time Clock (RTC)138 4.4 Operating System (OS) Timer142 4.5 Pulse Width Modulator148 4.6 System Integration Unit Register Summary151 DMA Controller 5183 Memory Controller 6265 LCD Controller 7311 Synchronous Serial Port Controller 8331 I2C Bus Interface Unit 9359 UARTs 10387 Fast Infrared Communication Port 11403 USB Device Controller 12453 AC97 Controller Unit 13489 Inter-Integrated-Circuit Sound (I2S) Controller 14505 MultiMediaCard Controller 15543 Network SSP Serial Port 16573 Hardware UART 17
598 pages 4.22 Mb
2 ii Intel PXA255 Processor Developers Manual3 Contents25 Introduction 11.1 Intel XScale Microarchitecture Features 1.2 System Integration Features26 1.2.1 Memory Controller1.2.2 Clocks and Power Controllers 1.2.3 Universal Serial Bus (USB) Client 27 1.2.4 DMA Controller (DMAC)1.2.5 LCD Controller 1.2.6 AC97 Controller 1.2.7 Inter-IC Sound (I2S) Controller 1.2.8 Multimedia Card (MMC) Controller 1.2.9 Fast Infrared (FIR) Communication Port 28 1.2.10 Synchronous Serial Protocol Controller (SSPC)1.2.11 Inter-Integrated Circuit (I2C) Bus Interface Unit 1.2.12 GPIO 1.2.13 UARTs1.2.13.1 Full Function UART (FFUART) 1.2.13.2 Bluetooth UART (BTUART) 1.2.13.3 Standard UART (STUART) 1.2.13.4 Hardware UART (HWUART) 29 1.2.14 Real-Time Clock (RTC)1.2.15 OS Timers 1.2.16 Pulse-Width Modulator (PWM) 1.2.17 Interrupt Control1.2.18 Network Synchronous Serial Protocol Port 31 System Architecture 263 Clocks and Power Manager 3105 System Integration Unit 4 4.1 General-Purpose I/O4.1.1 GPIO Operation 106 4.1.2 GPIO Alternate Functions110 4.1.3 GPIO Register Definitions 111 4.1.3.1 GPIO Pin-Level Registers (GPLR0, GPLR1, GPLR2)4-8 Intel PXA255 Processor Developer s Manual This is read/write register. Ignore reads from reserved bits. Wr ite zeros to reserved bits. 112 4.1.3.2 GPIO Pin Direction Registers (GPDR0, GPDR1, GPDR2)Table 4-4. GPLR1 Bit Definitions Table 4-5. GPLR2 Bit DefinitionsIntel PXA255 Processor Developers Manual 4-9 113 Table 4-6. GPDR0 Bit DefinitionsTable 4-7. GPDR1 Bit Definitions Table 4-8. GPDR2 Bit Definitions4-10 Intel PXA255 Processor De veloper s Manual 114 Table 4-10. GPSR1 Bit DefinitionsIntel PXA255 Processor Developers Manual 4-11 115 Table 4-11. GPSR2 Bit DefinitionsTable 4-12. GPCR0 Bit Definitions Table 4-13. GPCR1 Bit Definitions Intel PXA255 Processor Developers Manual 4-13 117 Table 4-15. GRER0 Bit DefinitionsTable 4-16. GRER1 Bit Definitions Table 4-17. GRER2 Bit Definitions4-14 Intel PXA255 Processor De veloper s Manual 118 Table 4-18. GFER0 Bit DefinitionsTable 4-19. GFER1 Bit Definitions Table 4-20. GFER2 Bit DefinitionsIntel PXA255 Processor Developers Manual 4-15 119 4.1.3.5 GPIO Edge Detect Status Register (GEDR0, GEDR1, GEDR2)Table 4-22. GEDR1 Bit Definitions 120 4.1.3.6 GPIO Alternate Function Register (GAFR0_L, GAFR0_U, GAFR1_L, GAFR1_U, GAFR2_L, GAFR2_U) 123 4.1.3.7 Example Procedure for Configuring the Alternate Function Registers 124 4.2 Interrupt Controller132 4.3 Real-Time Clock (RTC)138 4.4 Operating System (OS) Timer142 4.5 Pulse Width Modulator148 4.6 System Integration Unit Register Summary151 DMA Controller 5183 Memory Controller 6263 LCD Controller 7309 Synchronous Serial Port Controller 8329 I2C Bus Interface Unit 9357 UARTs 10385 Fast Infrared Communication Port 11401 USB Device Controller 12451 AC97 Controller Unit 13487 Inter-Integrated-Circuit Sound (I2S) Controller 14503 MultiMediaCard Controller 15541 Network SSP Serial Port 16571 Hardware UART 17
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