LAN9312

High Performance

Two Port 10/100 Managed

Ethernet Switch with 32-Bit

Non-PCI CPU Interface

PRODUCT FEATURES

Datasheet

Highlights

„ Ports

„High performance and full featured 2 port switch with VLAN, QoS packet prioritization, Rate Limiting, IGMP Snooping and management functions

„Easily interfaces to most 32-bit embedded CPU’s

„Unique Virtual PHY feature simplifies software development by mimicking the multiple switch ports as a single port MAC/PHY

„Integrated IEEE 1588 Hardware Time Stamp Unit

Target Applications

„Cable, satellite, and IP set-top boxes

„Digital televisions

„Digital video recorders

„VoIP/Video phone systems

„Home gateways

„Test/Measurement equipment

„Industrial automation systems

Key Benefits

„Ethernet Switch Fabric

—32K buffer RAM

—1K entry forwarding table

—Port based IEEE 802.1Q VLAN support (16 groups)

–Programmable IEEE 802.1Q tag insertion/removal

—IEEE 802.1d spanning tree protocol support

—QoS/CoS Packet prioritization

–4 dynamic QoS queues per port

–Input priority determined by VLAN tag, DA lookup, TOS, DIFFSERV or port default value

–Programmable class of service map based on input priority

–Remapping of 802.1Q priority field on per port basis

–Programmable rate limiting at the ingress/egress ports with random early discard, per port / priority

—IGMP v1/v2/v3 snooping for Multicast packet filtering

—IPV6 Multicast Listener Discovery snoop

—Programmable filter by MAC address

„Switch Management

—2 internal 10/100 PHYs with HP Auto-MDIX support

—Fully compliant with IEEE 802.3 standards

—10BASE-T and 100BASE-TX support

—Full and half duplex support

—Full duplex flow control

—Backpressure (forced collision) half duplex flow control

—Automatic flow control based on programmable levels

—Automatic 32-bit CRC generation and checking

—Automatic payload padding

—2K Jumbo packet support

—Programmable interframe gap, flow control pause value

—Full transmit/receive statistics

—Auto-negotiation

—Automatic MDI/MDI-X

—Loop-back mode

„High-performance host bus interface

—Provides in-band network communication path

—Access to management registers

—Simple, SRAM-like interface

—32-bit data bus

—Big, little, and mixed endian support

—Large TX and RX FIFO’s for high latency applications

—Programmable water marks and threshold levels

—Host interrupt support

„IEEE 1588 Hardware Time Stamp Unit

—Global 64-bit tunable clock

—Master or slave mode per port

—Time stamp on TX or RX of Sync and Delay_req packets per port, Timestamp on GPIO

—64-bit timer comparator event generation (GPIO or IRQ)

„Comprehensive Power Management Features

—Wake on LAN

—Wake on link status change (energy detect)

—Magic packet wakeup

—Wakeup indicator event signal

„Other Features

—General Purpose Timer

—Serial EEPROM interface (I2C master or MicrowireTM master) for non-managed configuration

—Programmable GPIOs/LEDs

„Single 3.3V power supply

„Available in Commercial Temp. Range

—Port mirroring/monitoring/sniffing: ingress and/or egress traffic on any ports or port pairs

—Fully compliant statistics (MIB) gathering counters

—Control registers configurable on-the-fly

SMSC LAN9312

DATASHEET

Revision 1.4 (08-19-08)