SMSC LAN9312 7.2.1100BASE-TXTransmit, 7.2.1.24B/5B Encoder, 7.2.1.1MII MAC Interface

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

7.2.1100BASE-TX Transmit

The 100BASE-TX transmit data path is shown in Figure 7.2. Shaded blocks are those which are internal to the PHY. Each major block is explained in the following sections.

		Internal			100M
	MII Transmit Clock				PLL
Port x
MAC
		Internal		MII MAC			25MHz		4B/5B	25MHz by	Scrambler
	MII 25 MHz by 4 bits			Interface			by 4 bits	Encoder		5 bits	and PISO
						125 Mbps Serial
NRZI		NRZI	MLT-3			MLT-3	100M		MLT-3	Magnetics
Converter			Converter				TX Driver
						MLT-3

RJ45 MLT-3 CAT-5

Figure 7.2 100BASE-TX Transmit Data Path

7.2.1.1MII MAC Interface

For a transmission, the switch fabric MAC drives the transmit data to the PHYs MII MAC Interface. The MII MAC Interface is described in detail in Section 7.2.7, "MII MAC Interface".

Note: The PHY is connected to the switch fabric MAC via standard MII signals. Refer to the IEEE

802.3specification for additional details.

7.2.1.24B/5B Encoder

The transmit data passes from the MII block to the 4B/5B Encoder. This block encodes the data from 4-bit nibbles to 5-bit symbols (known as “code-groups”) according to Table 7.2. Each 4-bit data-nibble is mapped to 16 of the 32 possible code-groups. The remaining 16 code-groups are either used for control information or are not valid.

The first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles, 0 through F. The remaining code-groups are given letter designations with slashes on either side. For example, an IDLE code-group is /I/, a transmit error code-group is /H/, etc.

Revision 1.4 (08-19-08)	84	SMSC LAN9312
	DATASHEET