High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

14.2.8.7Virtual PHY Auto-Negotiation Expansion Register (VPHY_AN_EXP)

Offset:

1D8h

Size:

32 bits

Index (decimal):

6

 

 

This register is used in the Auto-Negotiation process.

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

31:16

RESERVED

RO

-

 

(See Note 14.37)

 

 

 

 

 

 

15:5

RESERVED

RO

-

 

 

 

 

4

Parallel Detection Fault

RO

0b

 

This bit indicates whether a Parallel Detection Fault has been detected. This

 

Note 14.38

 

bit is always 0.

 

 

 

0: A fault hasn’t been detected via the Parallel Detection function

 

 

 

1: A fault has been detected via the Parallel Detection function

 

 

 

 

 

 

3

Link Partner Next Page Able

RO

0b

 

This bit indicates whether the link partner has next page ability. This bit is

 

Note 14.39

 

always 0.

 

 

 

0: Link partner does not contain next page capability

 

 

 

1: Link partner contains next page capability

 

 

 

 

 

 

2

Local Device Next Page Able

RO

0b

 

This bit indicates whether the local device has next page ability. This bit is

 

Note 14.39

 

always 0.

 

 

 

0: Local device does not contain next page capability

 

 

 

1: Local device contains next page capability

 

 

 

 

 

 

1

Page Received

RO/LH

1b

 

This bit indicates the reception of a new page.

 

Note 14.40

 

0: A new page has not been received

 

 

 

1: A new page has been received

 

 

 

 

 

 

0

Link Partner Auto-Negotiation Able

RO

1b

 

This bit indicates the Auto-negotiation ability of the link partner.

 

Note 14.41

 

0: Link partner is not Auto-Negotiation able

 

 

 

1: Link partner is Auto-Negotiation able

 

 

 

 

 

 

Note 14.37 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on a DWORD boundary. When accessed serially (through the MII management protocol), the register is 16-bits wide.

Note 14.38 Since the Virtual PHY link partner is emulated, there is never a Parallel Detection Fault and this bit is always 0.

Note 14.39 Next page ability is not supported by the Virtual PHY or emulated link partner.

Note 14.40 The page received bit is clear when read. It is first cleared on reset, but set shortly thereafter when the Auto-Negotiation process is run.

Note 14.41 The emulated link partner will show Auto-Negotiation able unless Auto-Negotiation fails (no common bits between the advertised ability and the link partner ability).

Revision 1.4 (08-19-08)

256

SMSC LAN9312

 

DATASHEET