High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
Figure 10.2 displays the various bus states of a typical I2C cycle.
data | data | data | data | data | data |
can | can | can | can | ||
change | stable | change | change | stable | change |
EE_SDA |
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S |
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EE_SCL |
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Start Condition | Data Valid |
| Data Valid | Stop Condition | |
or Ack | Condition |
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Figure 10.2 I2C Cycle
10.2.2.2I2C EEPROM Device AddressingThe I2C EEPROM is addressed for a read or write operation by first sending a control byte followed by the address byte or bytes. The control byte is preceded by a start condition. The control byte and address byte(s) are each acknowledged by the EEPROM slave. If the EEPROM slave fails to send an acknowledge, then the sequence is aborted and the EPC_TIMEOUT bit of the EEPROM Command Register (E2P_CMD) is set.
The control byte consists of a
Figure 10.3 illustrates typical I2C EEPROM addressing bit order for single and double byte addressing.
Control Byte
S | 1 | 0 | 1 | 0 | A | A | A | 0 | ||
01 | 9 | 8 | ||||||||
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Address Byte
A A A A A A A A A A CK 7 6 5 4 3 2 1 0 CK
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| Address High |
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| Address Low |
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| A |
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| Byte |
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| A |
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| Byte |
| A | ||||||||||||
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S | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | A | A | A | A | A | A | A | A | A |
| A | A | A | A | A | A | A | ||||||||||
C | 1 |
| 1 | 1 | 1 | 1 | 1 | 9 | 8 | C | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| 0 | C | |||||||||||||||
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| K | 5 |
| 4 | 3 | 2 | 1 | 0 | K |
| K | ||||||||||||
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Chip / Block R/~W | Chip / Block R/~W |
Select Bits | Select Bits |
Single Byte Addressing | Double Byte Addressing |
| Figure 10.3 I2C EEPROM Addressing |
SMSC LAN9312 | 141 | Revision 1.4 |
| DATASHEET |
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