High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

14.5.1.4Switch Global Interrupt Pending Register (SW_IPR)

Register #:

0005h

Size:

32 bits

This read-only register contains the pending global interrupts for the switch fabric. A set bit indicates an unmasked bit in the corresponding switch fabric sub-system has been triggered. All switch related interrupts in this register may be masked via the Switch Global Interrupt Mask Register (SW_IMR) register. When an unmasked switch fabric interrupt is generated in this register, the interrupt will trigger the SWITCH_INT bit in the Interrupt Status Register (INT_STS). Refer to Chapter 5, "System Interrupts," on page 49 for more information.

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

31:7

RESERVED

RO

-

 

 

 

 

6

Buffer Manager Interrupt (BM)

RC

0b

 

Set when any unmasked bit in the Buffer Manager Interrupt Pending

 

 

 

Register (BM_IPR) is triggered. This bit is cleared upon a read.

 

 

 

 

 

 

5

Switch Engine Interrupt (SWE)

RC

0b

 

Set when any unmasked bit in the Switch Engine Interrupt Pending Register

 

 

 

(SWE_IPR) is triggered. This bit is cleared upon a read.

 

 

 

 

 

 

4:3

RESERVED

RO

-

 

 

 

 

2

Port 2 MAC Interrupt (MAC_2)

RC

0b

 

Set when any unmasked bit in the MAC_IPR_2 register (see Section

 

 

 

14.5.2.44, on page 365) is triggered. This bit is cleared upon a read.

 

 

 

 

 

 

1

Port 1 MAC Interrupt (MAC_1)

RC

0b

 

Set when any unmasked bit in the MAC_IPR_1 register (see Section

 

 

 

14.5.2.44, on page 365) is triggered. This bit is cleared upon a read.

 

 

 

 

 

 

0

Port 0 MAC Interrupt (MAC_MII)

RC

0b

 

Set when any unmasked bit in the MAC_IPR_MII register (see Section

 

 

 

14.5.2.44, on page 365) is triggered. This bit is cleared upon a read.

 

 

 

 

 

 

SMSC LAN9312

321

Revision 1.4 (08-19-08)

 

DATASHEET