High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
BITS |
| DESCRIPTION | TYPE | DEFAULT |
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13 | Alternate MAC Address 1 Enable Port 0(Host MAC) | R/W | 0b | |
| (MAC_ALT1_EN_MII) |
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| This bit enables/disables the alternate MAC address 1 on Port 0. |
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| 0: Disables alternate MAC address on Port 0 |
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| 1: Enables MAC address 01:00:5E:00:01:82 as a PTP address on Port 0 |
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12 | Alternate MAC Address 2 Enable Port 0(Host MAC) | R/W | 0b | |
| (MAC_ALT2_EN_MII) |
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| This bit enables/disables the alternate MAC address 2 on Port 0. |
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| 0: Disables alternate MAC address on Port 0 |
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| 1: Enables MAC address 01:00:5E:00:01:83 as a PTP address on Port 0 |
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11 | Alternate MAC Address 3 Enable Port 0(Host MAC) | R/W | 0b | |
| (MAC_ALT3_EN_MII) |
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| This bit enables/disables the alternate MAC address 3 on Port 0. |
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| 0: Disables alternate MAC address on Port 0 |
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| 1: Enables MAC address 01:00:5E:00:01:84 as a PTP address on Port 0 |
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10 | User Defined MAC Address Enable Port 0(Host MAC) | R/W | 0b | |
| (MAC_USER_EN_MII) |
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| This bit enables/disables the auxiliary MAC address on Port 0. The auxiliary |
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| address is defined via the 1588_AUX_MAC_HI and 1588_AUX_MAC_LO |
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| registers. |
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| 0: Disables auxiliary MAC address on Port 0 |
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| 1: Enables auxiliary MAC address as a PTP address on Port 0 |
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9 | Lock Enable RX Port 0(Host MAC) (LOCK_RX_MII) | R/W | 1b | |
| This bit enables/disables the RX lock. This lock prevents a 1588 capture |
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| from overwriting the Clock, UUDI and Sequence ID values if the 1588 RX |
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| interrupt for Port 0 is ready set due to a previous capture. |
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| 0: Disables RX Port 0 Lock |
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| 1: Enables RX Port 0 Lock |
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| Note: | For Port 0, receive is defined as data from the switch fabric, while |
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| transmit is to the switch fabric. |
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8 | Lock Enable TX Port 0(Host MAC) (LOCK_TX_MII) | R/W | 1b | |
| This bit enables/disables the TX lock. This lock prevents a 1588 capture |
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| from overwriting the Clock, UUDI and Sequence ID values if the 1588 TX |
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| interrupt for Port 0 is ready set due to a previous capture. |
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| 0: Disables TX Port 0 Lock |
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| 1: Enables TX Port 0 Lock |
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| Note: | For Port 0, receive is defined as data from the switch fabric, while |
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| transmit is to the switch fabric. |
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7 | RESERVED | RO | - | |
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6 | Lock Enable GPIO 9 (LOCK_GPIO_9) | R/W | 1b | |
| This bit enables/disables the GPIO 9 lock. This lock prevents a 1588 capture |
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| from overwriting the Clock value if the 1588_GPIO9 interrupt in the 1588 |
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| Interrupt Status and Enable Register (1588_INT_STS_EN) is already set |
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| due to a previous capture. |
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| 0: Disables GPIO 9 Lock |
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| 1: Enables GPIO 9 Lock |
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Revision 1.4 | 224 | SMSC LAN9312 |
| DATASHEET |
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