High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

14.5.2.12Port x MAC Receive CRC Error Count Register (MAC_RX_CRCERR_CNT_x)

Register #:

Port0: 0419h

Size:

32 bits

 

Port1:

0819h

 

 

 

Port2:

0C19h

 

 

This register provides a counter of received packets that with CRC errors. The counter is cleared upon being read.

BITS

 

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

 

31:0

RX CRC

 

RC

00000000h

 

Count of packets that have between 64 and the maximum allowable number

 

 

 

of bytes and have a bad FCS, but do not have an extra nibble. The max

 

 

 

number of bytes is 1518 for untagged packets and 1522 for tagged packets.

 

 

 

If Jumbo2K (bit 3) is set in the Port x MAC Receive Configuration Register

 

 

 

(MAC_RX_CFG_x), the max number of bytes is 2048.

 

 

 

Note:

This counter will stop at its maximum value of FFFF_FFFFh.

 

 

 

 

Minimum rollover time at 100Mbps is approximately 137 hours.

 

 

 

 

 

 

 

SMSC LAN9312

333

Revision 1.4 (08-19-08)

 

DATASHEET