High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
4.2.2.2Soft Reset (SRST)
A soft reset is performed by setting the SRST bit of the Hardware Configuration Register (HW_CFG). A soft reset will reset the HBI, Host MAC, and System CSRs below address 100h. The soft reset also clears any TX or RX errors in the Host MAC transmitter and receiver (TXE/RXE). This reset does not latch the configuration straps. On soft reset, the EEPROM Loader is run, but loads only the MAC address into the Host MAC. No other values are loaded by the EEPROM Loader in this case.
A soft reset typically takes 590uS, plus an additional time (550uS for I2C, 170uS for Microwire) when data is loaded from the EEPROM via the EEPROM Loader.
4.2.3Single-Module Resets
A
4.2.3.1Port 2 PHY Reset
A Port 2 PHY reset is performed by setting the PHY2_RST bit of the Reset Control Register (RESET_CTL) or the Reset bit in the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x). Upon completion of the Port 2 PHY reset, the PHY2_RST and Reset bits are automatically cleared. No other modules of the LAN9312 are affected by this reset.
In addition to the methods above, the Port 2 PHY is automatically reset after returning from a PHY
Port 2 PHY reset completion can be determined by polling the PHY2_RST bit in the Reset Control Register (RESET_CTL) or the Reset bit in the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) until it clears. Under normal conditions, the PHY2_RST and Reset bit will clear approximately 110uS after the Port 2 PHY reset occurrence.
Note: When using the Reset bit to reset the Port 2 PHY, register bits designated as NASR are not reset.
Refer to Section 7.2.10, "PHY Resets," on page 95 for additional information on Port 2 PHY resets.
4.2.3.2Port 1 PHY Reset
A Port 1 PHY reset is performed by setting the PHY1_RST bit of the Reset Control Register (RESET_CTL) or the Reset bit in the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x). Upon completion of the Port 1 PHY reset, the PHY1_RST and Reset bits are automatically cleared. No other modules of the LAN9312 are affected by this reset.
In addition to the methods above, the Port 1 PHY is automatically reset after returning from a PHY
Port 1 PHY reset completion can be determined by polling the PHY1_RST bit in the Reset Control Register (RESET_CTL) or the Reset bit in the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) until it clears. Under normal conditions, the PHY1_RST and Reset bit will clear approximately 110uS after the Port 1 PHY reset occurrence.
SMSC LAN9312 | 39 | Revision 1.4 |
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