High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

6

MF Preamble Suppression

RO

0b

 

This bit indicates whether the Virtual PHY accepts management frames with

 

 

 

the preamble suppressed.

 

 

 

0: Management frames with preamble suppressed not accepted

 

 

 

1: Management frames with preamble suppressed accepted

 

 

 

 

 

 

5

Auto-Negotiation Complete

RO

1b

 

This bit indicates the status of the Auto-Negotiation process.

 

Note 14.20

 

0: Auto-Negotiation process not completed

 

 

 

1: Auto-Negotiation process completed

 

 

 

 

 

 

4

Remote Fault

RO

0b

 

This bit indicates if a remote fault condition has been detected.

 

Note 14.21

 

0: No remote fault condition detected

 

 

 

1: Remote fault condition detected

 

 

 

 

 

 

3

Auto-Negotiation Ability

RO

1b

 

This bit indicates the status of the Virtual PHY’s auto-negotiation.

 

 

 

0: Virtual PHY is unable to perform auto-negotiation

 

 

 

1: Virtual PHY is able to perform auto-negotiation

 

 

 

 

 

 

2

Link Status

RO

1b

 

This bit indicates the status of the link.

 

Note 14.21

 

0: Link is down

 

 

 

1: Link is up

 

 

 

 

 

 

1

Jabber Detect

RO

0b

 

This bit indicates the status of the jabber condition.

 

Note 14.21

 

0: No jabber condition detected

 

 

 

1: Jabber condition detected

 

 

 

 

 

 

0

Extended Capability

RO

1b

 

This bit indicates whether extended register capability is supported.

 

Note 14.22

 

0: Basic register set capabilities only

 

 

 

1: Extended register set capabilities

 

 

 

 

 

 

Note 14.17 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on a DWORD boundary. When accessed serially (through the MII management protocol), the register is 16-bits wide.

Note 14.18 The Virtual PHY supports 100BASE-X (half and full duplex) and 10BASE-T (half and full duplex) only. All other modes will always return as 0 (unable to perform).

Note 14.19 The Virtual PHY does not support Register 15 or 1000 Mb/s operation. Thus this bit is always returned as 0.

Note 14.20 The Auto-Negotiation Complete bit is first cleared on a reset, but set shortly after (when the Auto-Negotiation process is run). Refer to Section 7.3.1, "Virtual PHY Auto- Negotiation," on page 96 for additional details.

Note 14.21 The Virtual PHY never has remote faults, its link is always up, and does not detect jabber.

Note 14.22 The VIrtual PHY supports basic and some extended register capability. The Virtual PHY supports Registers 0-6 (per the IEEE 802.3 specification).

SMSC LAN9312

249

Revision 1.4 (08-19-08)

 

DATASHEET