High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

DIGITAL_RST, nRST,

POR, RELOAD

EPC_BUSY = 1

Read Byte 0

Byte 0 = A5h

N

Load PHY registers with

 

current straps

 

 

Y

Read Bytes 1-6

Write Bytes 1-6 into Host

MAC and switch MAC

Address Registers

Read Byte 7-11

Byte 7 = A5h

N

 

Load PHY registers with

 

 

 

 

current straps

 

 

 

 

 

 

 

 

Y

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Bytes 8-11 into

 

 

 

 

 

Configuration Strap

 

 

 

 

 

registers

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Update PHY registers

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Update VPHY registers

Update LED_CFG,

MANUAL_FC_1,

MANUAL_FC_2 and

MANUAL_FC_mii

registers

Read Byte 12

Byte 12 = A5h

N

 

Y

Perform register data load loop

EPC_BUSY = 0

Soft Reset

N

 

Y

EPC_BUSY = 1

Read Byte 0

Byte 0 = A5h

N

 

Y

Read Bytes 1-6

Write Bytes 1-6 into Host MAC Address Registers

Figure 10.14 EEPROM Loader Flow Diagram

Revision 1.4 (08-19-08)

150

SMSC LAN9312

 

DATASHEET