High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
Chapter 14 Register Descriptions
This section describes the various LAN9312 control and status registers (CSR’s). These registers are broken into 5 categories. The following sections detail the functionality and accessibility of all the LAN9312 registers within each category:
Section 14.1, "TX/RX FIFO Ports," on page 167
Section 14.2, "System Control and Status Registers," on page 168
Section 14.3, "Host MAC Control and Status Registers," on page 269
Section 14.4, "Ethernet PHY Control and Status Registers," on page 285
Section 14.5, "Switch Fabric Control and Status Registers," on page 307
Figure 14.1 contains an overall base register memory map of the LAN9312. This memory map is not drawn to scale, and should be used for general reference only.
Note: Register bit type definitions are provided in Section 1.3, "Register Nomenclature," on page 19.
Note: Not all LAN9312 registers are memory mapped or directly addressable. For details on the accessibility of the various LAN9312 registers, refer the register
3FFh |
| |
... | RESERVED | |
2E0h |
| |
2DCh | Switch CSR Direct Data | |
... | ||
Registers | ||
200h |
| |
1DCh |
| |
Virtual PHY Registers | ||
1C0h | ||
| ||
1B0h |
| |
Switch Interface Registers | ||
1ACh |
| |
19Ch | 1588 Registers | |
| ||
100h |
| |
0A8h |
| |
Host MAC Interface Registers | ||
0A4h |
| |
050h |
| |
04Ch | TX Status FIFO PEEK | |
048h | TX Status FIFO Port | |
044h | RX Status FIFO PEEK | |
040h | RX Status FIFO Port | |
03Ch | TX Data FIFO Port | |
020h | & Alias Ports | |
01Ch | RX Data FIFO Port | |
Base + 000h | & Alias Ports | |
|
|
CSRs System
FIFOs TX/RX
Figure 14.1 LAN9312 Base Register Memory Map
Revision 1.4 | 166 | SMSC LAN9312 |
| DATASHEET |
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