High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

14.4.2.6Port x PHY Auto-Negotiation Link Partner Base Page Ability Register (PHY_AN_LP_BASE_ABILITY_x)

Index (decimal): 5

Size:

16 bits

This read-only register contains the advertised ability of the link partner’s PHY and is used in the Auto- Negotiation process between the link partner and the Port x PHY.

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

15

Next Page

RO

0b

 

This bit indicates the link partner PHY page capability.

 

 

 

0: Link partner PHY does not advertise next page capability

 

 

 

1: Link partner PHY advertises next page capability

 

 

 

 

 

 

14

Acknowledge

RO

0b

 

This bit indicates whether the link code word has been received from the

 

 

 

partner.

 

 

 

0: Link code word not yet received from partner

 

 

 

1: Link code word received from partner

 

 

 

 

 

 

13

Remote Fault

RO

0b

 

This bit indicates whether a remote fault has been detected.

 

 

 

0: No remote fault

 

 

 

1: Remote fault detected

 

 

 

 

 

 

12

RESERVED

RO

-

 

 

 

 

11

Asymmetric Pause

RO

0b

 

This bit indicates the link partner PHY asymmetric pause capability.

 

 

 

0: No Asymmetric PAUSE toward link partner

 

 

 

1: Asymmetric PAUSE toward link partner

 

 

 

 

 

 

10

Pause

RO

0b

 

This bit indicates the link partner PHY symmetric pause capability.

 

 

 

0: No Symmetric PAUSE toward link partner

 

 

 

1: Symmetric PAUSE toward link partner

 

 

 

 

 

 

9

100BASE-T4

RO

0b

 

This bit indicates the link partner PHY 100BASE-T4 capability.

 

 

 

0: 100BASE-T4 ability not supported

 

 

 

1: 100BASE-T4 ability supported

 

 

 

 

 

 

8

100BASE-X Full Duplex

RO

0b

 

This bit indicates the link partner PHY 100BASE-X full duplex capability.

 

 

 

0: 100BASE-X full duplex ability not supported

 

 

 

1: 100BASE-X full duplex ability supported

 

 

 

 

 

 

7

100BASE-X Half Duplex

RO

0b

 

This bit indicates the link partner PHY 100BASE-X half duplex capability.

 

 

 

0: 100BASE-X half duplex ability not supported

 

 

 

1: 100BASE-X half duplex ability supported

 

 

 

 

 

 

Revision 1.4 (08-19-08)

296

SMSC LAN9312

 

DATASHEET