High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
14.5.4.26Buffer Manager Interrupt Mask Register (BM_IMR)Register #: | 1C20h | Size: | 32 bits |
This register contains the Buffer Manager interrupt mask, which masks the interrupts in the Buffer Manager Interrupt Pending Register (BM_IPR). All Buffer Manager interrupts are masked by setting the Interrupt Mask bit. Clearing this bit will unmask the interrupts. Refer to Chapter 5, "System Interrupts," on page 49 for more information.
BITS | DESCRIPTION | TYPE | DEFAULT |
|
|
|
|
31:1 | RESERVED | RO | - |
|
|
|
|
0 | Interrupt Mask | R/W | 1b |
| When set, this bit masks interrupts from the Buffer Manager. The status bits |
|
|
| in the Buffer Manager Interrupt Pending Register (BM_IPR) are not affected. |
|
|
|
|
|
|
SMSC LAN9312 | 437 | Revision 1.4 |
| DATASHEET |
|