SMSC LAN9312 15.5.9TX Data FIFO Direct PIO Write Cycle Timing

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

15.5.9TX Data FIFO Direct PIO Write Cycle Timing

Please refer to Section 8.4.9, "TX Data FIFO Direct PIO Writes," on page 111 for a functional description of this mode.

FIFO_SEL

A[2], END_SEL

tcycle

tasu tah

tcsltcsh

nCS, nWR

tdsutdh

D[31:0]

Figure 15.9 TX Data FIFO Direct PIO Write Cycle Timing

Table 15.13 TX Data FIFO Direct PIO Write Cycle Timing Values

SYMBOL	DESCRIPTION	MIN	TYP	MAX	UNITS
tcycle	Write Cycle Time	45			nS
tcsl	nCS, nWER Assertion Time	32			nS
tcsh	nCS, nWR De-assertion Time	13			nS
tasu	Address, FIFO_SEL Setup to nCS, nWR Assertion	0			nS
tah	Address, FIFO_SEL Hold Time	0			nS
tdsu	Data Setup to nCS, nWR De-assertion	7			nS
tdh	Data Hold Time	0			nS

Note: A TX Data FIFO direct PIO write cycle begins when both nCS and nWR are asserted. The cycle ends when either or both nCS and nWR are de-asserted. They may be asserted and de- asserted in any order.

SMSC LAN9312	451	Revision 1.4 (08-19-08)
	DATASHEET