High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
14.2System Control and Status Registers
The System CSR’s are directly addressable memory mapped registers with a base address offset range of 050h to 2DCh. These registers are addressable by the Host via the Host Bus Interface (HBI).
Table 14.1 lists the System CSR’s and their corresponding addresses in order. All system CSR’s are reset to their default value on the assertion of a
The System CSR’s can be divided into 9
Section 14.2.1, "Interrupts," on page 172
Section 14.2.2, "Host MAC & FIFO’s," on page 180
Section 14.2.3, "GPIO/LED," on page 192
Section 14.2.4, "EEPROM," on page 197
Section 14.2.5, "IEEE 1588," on page 201
Section 14.2.6, "Switch Fabric," on page 229
Section 14.2.7, "PHY Management Interface (PMI)," on page 243
Section 14.2.8, "Virtual PHY," on page 245
Section 14.2.9, "Miscellaneous," on page 259
Table 14.1 System Control and Status Registers
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OFFSET | SYMBOL | REGISTER NAME |
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050h | ID_REV | Chip ID and Revision Register, Section 14.2.9.1 |
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054h | IRQ_CFG | Interrupt Configuration Register, Section 14.2.1.1 |
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058h | INT_STS | Interrupt Status Register, Section 14.2.1.2 |
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05Ch | INT_EN | Interrupt Enable Register, Section 14.2.1.3 |
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060h | RESERVED | Reserved for Future Use |
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064h | BYTE_TEST | Byte Order Test Register, Section 14.2.9.2 |
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068h | FIFO_INT | FIFO Level Interrupts Register, Section 14.2.1.4 |
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06Ch | RX_CFG | Receive Configuration Register, Section 14.2.2.1 |
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070h | TX_CFG | Transmit Configuration Register, Section 14.2.2.2 |
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074h | HW_CFG | Hardware Configuration Register, Section 14.2.9.3 |
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078h | RX_DP_CTRL | RX Datapath Control Register, Section 14.2.2.3 |
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07Ch | RX_FIFO_INF | Receive FIFO Information Register,Section 14.2.2.4 |
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080h | TX_FIFO_INF | Transmit FIFO Information Register, Section 14.2.2.5 |
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084h | PMT_CTRL | Power Management Control Register, Section 14.2.9.4 |
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088h | RESERVED | Reserved for Future Use |
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08Ch | GPT_CFG | General Purpose Timer Configuration Register, |
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090h | GPT_CNT | General Purpose Timer Count Register, Section 14.2.9.6 |
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094h - 098h | RESERVED | Reserved for Future Use |
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Revision 1.4 | 168 | SMSC LAN9312 |
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