High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
Chapter 1 Preface
1.1General Terms
100BT | |
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ADC | |
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ALR | Address Logic Resolution |
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BLW | Baseline Wander |
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BM | Buffer Manager - Part of the switch fabric |
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BPDU | Bridge Protocol Data Unit - Messages which carry the Spanning Tree |
| Protocol information |
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Byte | |
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CSMA/CD | Carrier Sense Multiple Access / Collision Detect |
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CSR | Control and Status Registers |
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CTR | Counter |
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DA | Destination Address |
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DWORD | |
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EPC | EEPROM Controller |
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FCS | Frame Check Sequence - The extra checksum characters added to the end |
| of an Ethernet frame, used for error detection and correction. |
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FIFO | First In First Out buffer |
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FSM | Finite State Machine |
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GPIO | General Purpose I/O |
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HBI | Host Bus Interface. The physical bus connecting the LAN9312 to the host. |
| Also referred to as the Host Bus. |
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HBIC | Host Bus Interface Controller. The hardware module that interfaces the |
| LAN9312 to the HBI. |
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Host | External system (Includes processor, application software, etc.) |
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IGMP | Internet Group Management Protocol |
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Inbound | Refers to data input to the LAN9312 from the host |
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This type of status bit is set whenever the condition that it represents is | |
| asserted. The bit remains set until the condition is no longer true, and the |
| status bit is cleared by writing a zero. |
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lsb | Least Significant Bit |
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LSB | Least Significant Byte |
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MDI | Medium Dependant Interface |
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MDIX | Media Independent Interface with Crossover |
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Revision 1.4 | 16 | SMSC LAN9312 |
| DATASHEET |
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