High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

5.2.8Software Interrupt

A general purpose software interrupt is provided in the top level Interrupt Status Register (INT_STS) and Interrupt Enable Register (INT_EN). The SW_INT interrupt (bit 31) of the Interrupt Status Register (INT_STS) is generated when SW_INT_EN (bit 31) of the Interrupt Enable Register (INT_EN) is set. This interrupt provides an easy way for software to generate an interrupt, and is designed for general software usage.

5.2.9Device Ready Interrupt

A device ready interrupt is provided in the top-level Interrupt Status Register (INT_STS) and Interrupt Enable Register (INT_EN). The READY interrupt (bit 30) of the Interrupt Status Register (INT_STS) indicates that the LAN9312 is ready to be accessed after a power-up or reset condition. Writing a 1 to this bit in the Interrupt Status Register (INT_STS) will clear it.

In order for a device ready interrupt event to trigger the external IRQ interrupt pin, bit 30 of the Interrupt Enable Register (INT_EN) must be set, and IRQ output must be enabled via bit 8 (IRQ_EN) of the Interrupt Configuration Register (IRQ_CFG).

Revision 1.4 (08-19-08)

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SMSC LAN9312

 

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