High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

4

IRQ Polarity (IRQ_POL)

R/W

0b

 

When cleared, this bit enables the IRQ line to function as an active low

NASR

 

 

output. When set, the IRQ output is active high. When the IRQ is configured

Note 14.1

 

 

as an open-drain output (via the IRQ_TYPE bit), this bit is ignored, and the

 

 

 

interrupt is always active low.

 

 

 

0: IRQ active low output

 

 

 

1: IRQ active high output

 

 

 

 

 

 

3:1

RESERVED

RO

-

 

 

 

 

0

IRQ Buffer Type (IRQ_TYPE)

R/W

0b

 

When this bit is cleared, the IRQ pin functions as an open-drain output for

NASR

 

 

use in a wired-or interrupt configuration. When set, the IRQ is a push-pull

Note 14.1

 

 

driver.

 

 

 

Note: When configured as an open-drain output, the IRQ_POL bit is

 

 

 

ignored and the interrupt output is always active low.

 

 

 

0: IRQ pin open-drain output

 

 

 

1: IRQ pin push-pull driver

 

 

 

 

 

 

Note 14.1 Register bits designated as NASR are not reset when either the SRST bit in the Hardware Configuration Register (HW_CFG) register or the DIGITAL_RST bit in the Reset Control Register (RESET_CTL) is set.

SMSC LAN9312

173

Revision 1.4 (08-19-08)

 

DATASHEET