SMSC LAN9312 14.2.5.171588 Clock Target Low-DWORDRegister (1588_CLOCK_TARGET_LO)

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

14.2.5.171588 Clock Target Low-DWORD Register (1588_CLOCK_TARGET_LO)

Offset: 180h Size: 32 bits

This read/write register combined with 1588 Clock Target High-DWORD Register (1588_CLOCK_TARGET_HI) form the 64-bit 1588 Clock Target value. The 1588 Clock Target value is compared to the current 1588 Clock value and can be used to trigger an interrupt upon at match. Refer to Chapter 11, "IEEE 1588 Hardware Time Stamp Unit," on page 154 for additional information.

BITS	DESCRIPTION	TYPE	DEFAULT
31:0	Clock Target Low (CLOCK_TARGET_LO)	R/W	00000000h
	This field contains the low 32-bits of the 64-bit 1588 Clock Compare value.

Note: Both this register and the 1588 Clock Target High-DWORD Register (1588_CLOCK_TARGET_HI) must be written for either to be affected.

SMSC LAN9312	217	Revision 1.4 (08-19-08)
	DATASHEET