High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

14.5.3.7Switch Engine ALR Configuration Register (SWE_ALR_CFG)

Register #:

1809h

Size:

32 bits

This register controls the ALR aging timer duration.

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

31:1

RESERVED

RO

-

 

 

 

 

0

ALR Age Test

R/W

0b

 

When set, this bit decreases the aging timer from 5 minutes to 50mS.

 

 

 

 

 

 

Revision 1.4 (08-19-08)

374

SMSC LAN9312

 

DATASHEET