High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
The Port x PHY
The Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x) is written with the new defaults as detailed in Section 14.4.2.9, "Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x)," on page 300.
The Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) is written with the new defaults as detailed in Section 14.4.2.1, "Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x)," on page 287. Additionally, the Restart
Note: Each of these PHY registers is written in its entirety, overwriting any previously changed bits.
10.2.4.4.2VIRTUAL PHY REGISTERS SYNCHRONIZATION
Some PHY register defaults are based on configuration straps. In order to maintain consistency between the updated configuration strap registers and the Virtual PHY registers, the Virtual PHY Auto- Negotiation Advertisement Register (VPHY_AN_ADV), Virtual PHY Special Control/Status Register (VPHY_ SPECIAL _ CONTROL _ STATUS) , and Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) are written when the EEPROM Loader is run.
The Virtual PHY
The Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS) is written with the new defaults as detailed in Section 14.2.8.8, "Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS)," on page 257.
The Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) is written with the new defaults as detailed in Section 14.2.8.1, "Virtual PHY Basic Control Register (VPHY_BASIC_CTRL)," on page 246. Additionally, the Restart
Note: Each of these VPHY registers is written in its entirety, overwriting any previously changed bits.
10.2.4.4.3LED AND MANUAL FLOW CONTROL REGISTER SYNCHRONIZATION
Since the defaults of the LED Configuration Register (LED_CFG), Port 1 Manual Flow Control Register (MANUAL_FC_1), Port 2 Manual Flow Control Register (MANUAL_FC_2), and Port 0(Host MAC) Manual Flow Control Register (MANUAL_FC_MII) are based on configuration straps, the EEPROM Loader reloads these registers with their new default values.
10.2.4.5Register DataOptionally following the configuration strap values, the EEPROM data may be formatted to allow access to the LAN9312 parallel, directly writable registers. Access to indirectly accessible registers (e.g. Switch Engine registers, etc.) is achievable with an appropriate sequence of writes (at the cost of EEPROM space).
This data is first preceded with a Burst Sequence Valid Flag (EEPROM byte 12). If this byte has a value of A5h, the data that follows is recognized as a sequence of bursts. Otherwise, the EEPROM Loader is finished, will go into a wait state, and clear the EPC_BUSY bit in the EEPROM Command Register (E2P_CMD). This can optionally generate an interrupt.
The data at EEPROM byte 13 and above should be formatted in a sequence of bursts. The first byte is the total number of bursts. Following this is a series of bursts, each consisting of a starting address, count, and the count x 4 bytes of data. This results in the following formula for formatting register data:
Revision 1.4 | 152 | SMSC LAN9312 |
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