High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

14.2.2.3Receive Datapath Control Register (RX_DP_CTRL)

Offset:

078h

Size:

32 bits

This register is used to discard unwanted receive frames.

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

31

RX Data FIFO Fast Forward (RX_FFWD)

R/W

0h

 

Writing a 1 to this bit causes the RX Data FIFO to fast-forward to the start

SC

 

 

of the next frame. This bit will remain high until the RX Data FIFO fast-

 

 

 

forward operation has completed. No reads should be issued to the RX Data

 

 

 

FIFO while this bit is high.

 

 

 

Note: Please refer to section Section 9.9.1.1, "Receive Data FIFO Fast

 

 

 

Forward," on page 134 for detailed information regarding the use

 

 

 

of RX_FFWD.

 

 

 

 

 

 

30:0

RESERVED

RO

-

 

 

 

 

SMSC LAN9312

183

Revision 1.4 (08-19-08)

 

DATASHEET