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High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
14.2.6.8Switch Fabric CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA)
Offset: | 200h - 2DCh | Size: | 32 bits |
This
Writes within the Switch Fabric CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA) address range automatically set the appropriate address, set the four byte enable bits, clear the R/nW bit and set the Busy bit in the Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD). The completion of the write cycle is indicated when the Busy bit is cleared. The address that is set in the Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) is mapped via Table 14.3. For more information on this method of writing to the Switch Fabric CSR’s, refer to Section 6.2.3, "Flow Control Enable Logic," on page 58.
BITS | DESCRIPTION | TYPE | DEFAULT |
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31:0 | Switch CSR Data (CSR_DATA) | WO | 00000000h |
| This field contains the value to be written to the corresponding Switch Fabric |
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Note: This set of registers is for write operations only. Reads can be performed via the Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) and Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA) registers only.
Table 14.3 Switch Fabric CSR to SWITCH_CSR_DIRECT_DATA Address Range Map
| SWITCH FABRIC CSR | SWITCH_CSR_DIRECT_DATA |
REGISTER NAME | REGISTER # | ADDRESS |
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| General Switch CSRs |
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SW_RESET | 0001h | 200h |
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SW_IMR | 0004h | 204h |
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| Switch Port 0 CSRs |
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MAC_RX_CFG_MII | 0401h | 208h |
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MAC_TX_CFG_MII | 0440h | 20Ch |
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MAC_TX_FC_SETTINGS_MII | 0441h | 210h |
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MAC_IMR_MII | 0480h | 214h |
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| Switch Port 1 CSRs |
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MAC_RX_CFG_1 | 0801h | 218h |
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MAC_TX_CFG_1 | 0840h | 21Ch |
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MAC_TX_FC_SETTINGS_1 | 0841h | 220h |
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MAC_IMR_1 | 0880h | 224h |
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| Switch Port 2 CSRs |
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MAC_RX_CFG_2 | 0C01h | 228h |
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Revision 1.4 | 240 | SMSC LAN9312 |
| DATASHEET |
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