High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

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Destination Address Source Address ……………FF FF FF FF FF FF

00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55

00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55

00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55

00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55

…CRC

Note: The switch fabric must be configured to pass magic packets to the Host MAC for this function to operate properly.

9.6Host MAC Address

The Host MAC address is configured via the Host MAC Address Low Register (HMAC_ADDRL) and Host MAC Address High Register (HMAC_ADDRH). These registers contain the 48-bit physical address of the Host MAC. The contents of these registers may be loaded directly by the host, or optionally, by the EEPROM Loader from EEPROM at power-on (if a programmed EEPROM is detected). The MAC address value loaded by the EEPROM Loader into the Host MAC address registers (for host packet unicast qualification), is also loaded into the Switch Fabric MAC address registers (for pause packet / flow control): Switch Fabric MAC Address Low Register (SWITCH_MAC_ADDRL) and Switch Fabric MAC Address High Register (SWITCH_MAC_ADDRH). These two sets of registers are loaded simultaneously via the same EEPROM byte addresses.

Table 9.7 below illustrates the byte ordering of the HMAC_ADDRL/SWITCH_MAC_ADDRL and HMAC_ADDRH/SWITCH_MAC_ADDRH registers with respect to the reception of the Ethernet physical address. Also shown is the correlation between the EEPROM addresses and HMAC_ADDRL/SWITCH_MAC_ADDRL and HMAC_ADDRH/SWITCH_MAC_ADDRH registers.

Table 9.7 EEPROM Byte Ordering and Register Correlation

EEPROM Address

Register Locations Written

Order of Reception on Ethernet

 

 

 

01h

HMAC_ADDRL[7:0]

1st

 

SWITCH_MAC_ADDRL[7:0]

 

 

 

 

02h

HMAC_ADDRL[15:8]

2nd

 

SWITCH_MAC_ADDRL[15:8]

 

 

 

 

03h

HMAC_ADDRL[23:16]

3rd

 

SWITCH_MAC_ADDRL[23:16]

 

 

 

 

04h

HMAC_ADDRL[31:24]

4th

 

SWITCH_MAC_ADDRL[31:24]

 

 

 

 

05h

HMAC_ADDRH[7:0]

5th

 

SWITCH_MAC_ADDRH[7:0]

 

 

 

 

06h

HMAC_ADDRH[15:8]

6th

 

SWITCH_MAC_ADDRH[15:8]

 

 

 

 

For example, if the desired Ethernet physical address is 12-34-56-78-9A-BC, the HMAC_ADDRL and HMAC_ADDRH registers would be programmed as shown in Figure 9.2. The values required to automatically load this configuration from the EEPROM are also shown.

SMSC LAN9312

119

Revision 1.4 (08-19-08)

 

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