High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
14.5.3.15Switch Engine DIFFSERV Table Command Status Register (SWE_DIFFSERV_TBL_CMD_STS)
Register #: | 1814h | Size: | 32 bits |
This register indicates the current DIFFSERV command status.
BITS | DESCRIPTION | TYPE | DEFAULT |
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31:1 | RESERVED | RO | - |
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0 | Operation Pending | RO | 0b |
| When set, this bit indicates that the read or write command is taking place. | SC |
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| This bit is cleared once the command has finished. |
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Revision 1.4 | 382 | SMSC LAN9312 |
| DATASHEET |
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