High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued)

REGISTER #

SYMBOL

REGISTER NAME

 

 

 

0414h

MAC_RX_256_TO_511_CNT_MII

Port 0 MAC Receive 256 to 511 Byte Count Register,

 

 

Section 14.5.2.7

 

 

 

0415h

MAC_RX_512_TO_1023_CNT_MII

Port 0 MAC Receive 512 to 1023 Byte Count Register,

 

 

Section 14.5.2.8

 

 

 

0416h

MAC_RX_1024_TO_MAX_CNT_MII

Port 0 MAC Receive 1024 to Max Byte Count Register,

 

 

Section 14.5.2.9

 

 

 

0417h

MAC_RX_OVRSZE_CNT_MII

Port 0 MAC Receive Oversize Count Register,

 

 

Section 14.5.2.10

 

 

 

0418h

MAC_RX_PKTOK_CNT_MII

Port 0 MAC Receive OK Count Register, Section 14.5.2.11

 

 

 

0419h

MAC_RX_CRCERR_CNT_MII

Port 0 MAC Receive CRC Error Count Register,

 

 

Section 14.5.2.12

 

 

 

041Ah

MAC_RX_MULCST_CNT_MII

Port 0 MAC Receive Multicast Count Register,

 

 

Section 14.5.2.13

 

 

 

041Bh

MAC_RX_BRDCST_CNT_MII

Port 0 MAC Receive Broadcast Count Register,

 

 

Section 14.5.2.14

 

 

 

041Ch

MAC_RX_PAUSE_CNT_MII

Port 0 MAC Receive Pause Frame Count Register,

 

 

Section 14.5.2.15

 

 

 

041Dh

MAC_RX_FRAG_CNT_MII

Port 0 MAC Receive Fragment Error Count Register,

 

 

Section 14.5.2.16

 

 

 

041Eh

MAC_RX_JABB_CNT_MII

Port 0 MAC Receive Jabber Error Count Register,

 

 

Section 14.5.2.17

 

 

 

041Fh

MAC_RX_ALIGN_CNT_MII

Port 0 MAC Receive Alignment Error Count Register,

 

 

Section 14.5.2.18

 

 

 

0420h

MAC_RX_PKTLEN_CNT_MII

Port 0 MAC Receive Packet Length Count Register,

 

 

Section 14.5.2.19

 

 

 

0421h

MAC_RX_GOODPKTLEN_CNT_MII

Port 0 MAC Receive Good Packet Length Count Register,

 

 

Section 14.5.2.20

 

 

 

0422h

MAC_RX_SYMBL_CNT_MII

Port 0 MAC Receive Symbol Error Count Register,

 

 

Section 14.5.2.21

 

 

 

0423h

MAC_RX_CTLFRM_CNT_MII

Port 0 MAC Receive Control Frame Count Register,

 

 

Section 14.5.2.22

 

 

 

0424h-043Fh

RESERVED

Reserved for Future Use

 

 

 

0440h

MAC_TX_CFG_MII

Port 0 MAC Transmit Configuration Register, Section 14.5.2.23

 

 

 

0441h

MAC_TX_FC_SETTINGS_MII

Port 0 MAC Transmit Flow Control Settings Register,

 

 

Section 14.5.2.24

 

 

 

0442h-0450h

RESERVED

Reserved for Future Use

 

 

 

0451h

MAC_TX_DEFER_CNT_MII

Port 0 MAC Transmit Deferred Count Register,

 

 

Section 14.5.2.25

 

 

 

0452h

MAC_TX_PAUSE_CNT_MII

Port 0 MAC Transmit Pause Count Register, Section 14.5.2.26

 

 

 

0453h

MAC_TX_PKTOK_CNT_MII

Port 0 MAC Transmit OK Count Register, Section 14.5.2.27

 

 

 

0454h

MAC_TX_64_CNT_MII

Port 0 MAC Transmit 64 Byte Count Register, Section 14.5.2.28

 

 

 

Revision 1.4 (08-19-08)

308

SMSC LAN9312

 

DATASHEET