High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

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Table 3.7 Miscellaneous Pins (continued)

 

 

 

 

 

BUFFER

 

PIN

 

NAME

SYMBOL

 

TYPE

DESCRIPTION

 

 

 

 

 

 

 

75

 

Test 1

TEST1

 

AI

Test 1: This pin must be tied to VDD33IO for

 

 

 

 

 

proper operation.

 

 

 

 

 

 

 

108

 

Test 2

TEST2

 

AI

Test 2: This pin must be tied to VDD33IO for

 

 

 

 

 

proper operation.

 

 

 

 

 

 

 

 

 

Power

PME

 

O8/OD8

Power Management Event: When programmed

 

 

Management

 

 

 

accordingly, this signal is asserted upon detection

 

 

Event

 

 

 

of a wakeup event. The polarity and buffer type of

 

 

 

 

 

 

this signal is programmable via the PME_EN bit of

62

 

 

 

 

 

the Power Management Control Register

 

 

 

 

 

(PMT_CTRL).

 

 

 

 

 

 

Refer to Chapter 4, "Clocking, Resets, and Power

 

 

 

 

 

 

Management," on page 36 for additional

 

 

 

 

 

 

information on the LAN9312 power management

 

 

 

 

 

 

features.

 

 

 

 

 

 

 

Note 3.7 The input buffers are enabled when configured as GPIO inputs only.

 

 

 

 

Table 3.8 PLL Pins

 

 

 

 

 

 

 

 

 

 

 

 

BUFFER

 

PIN

 

NAME

SYMBOL

 

TYPE

DESCRIPTION

 

 

 

 

 

 

 

 

 

PLL +1.8V

VDD18PLL

 

P

PLL +1.8V Power Supply: This pin must be

107

 

Power Supply

 

 

 

connected to VDD18CORE for proper operation.

 

 

 

 

 

Refer to the LAN9312 application note for

 

 

 

 

 

 

 

 

 

 

 

 

additional connection information.

 

 

 

 

 

 

 

 

 

Crystal Input

XI

 

ICLK

Crystal Input: External 25MHz crystal input. This

105

 

 

 

 

 

signal can also be driven by a single-ended clock

 

 

 

 

 

oscillator. When this method is used, XO should be

 

 

 

 

 

 

 

 

 

 

 

 

left unconnected.

 

 

 

 

 

 

 

106

 

Crystal

XO

 

OCLK

Crystal Output: External 25MHz crystal output.

 

Output

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 3.9 Core and I/O Power and Ground Pins

 

 

 

 

 

 

 

 

 

 

 

 

BUFFER

 

PIN

 

NAME

SYMBOL

 

TYPE

DESCRIPTION

 

 

 

 

 

 

 

7,13,21,27,

 

+3.3V I/O

VDD33IO

 

P

+3.3V Power Supply for I/O Pins and Internal

33,39,46,

 

Power

 

 

 

Regulator

54,64,66,

 

 

 

 

 

Refer to the LAN9312 application note for

72,73,81,

 

 

 

 

 

 

 

 

 

 

additional connection information.

87,93,100

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Digital Core

VDD18CORE

 

P

Digital Core +1.8V Power Supply Output: +1.8V

 

 

+1.8V Power

 

 

 

power from the internal core voltage regulator. All

3,14,40,65,

 

Supply

 

 

 

VDD18CORE pins must be tied together for proper

 

Output

 

 

 

operation.

74,88,104

 

 

 

 

 

 

 

 

 

 

Refer to the LAN9312 application note for

 

 

 

 

 

 

 

 

 

 

 

 

additional connection information.

 

 

 

 

 

 

 

Revision 1.4 (08-19-08)

34

SMSC LAN9312

 

DATASHEET