High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
14.4.2.10Port x PHY Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x)
Index (decimal): 27 | Size: | 16 bits |
This read/write register is used to control various options of the Port x PHY.
BITS | DESCRIPTION | TYPE | DEFAULT |
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15 | R/W | 0b | |
| This bit is responsible for determining the source of | NASR |
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| Port x. When set, the Manual MDIX and Auto MDIX straps |
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| (manual_mdix_strap_1/auto_mdix_strap_1 for Port 1 PHY, |
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| manual_mdix_strap_2/auto_mdix_strap_2 for Port 2 PHY) are overridden, |
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| and |
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| (AMDIXSTATE) of this register. When cleared, |
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| controlled by the Manual MDIX and Auto MDIX straps by default. Refer to |
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| Section 4.2.4, "Configuration Straps," on page 40 for configuration strap |
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| definitions. |
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| 0: Port x |
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| 1: Port x |
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14 | R/W | 0b | |
| When bit 15 (AMDIXCTRL) of this register is set, this bit is used in | NASR |
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| conjunction with bit 13 |
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| functionality as shown in Table 14.11. |
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13 | R/W | 0b | |
| When bit 15 (AMDIXCTRL) of this register is set, this bit is used in | NASR |
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| conjunction with bit 14 |
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| functionality as shown in Table 14.11. |
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12 | RESERVED | RO | - |
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11 | SQE Test Disable (SQEOFF) | R/W | 0b |
| This bit controls the disabling of the SQE test (Heartbeat). SQE test is | NASR |
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| enabled by default. |
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| 0: SQE test enabled |
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| 1: SQE test disabled |
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10 | Receive PLL Lock Control (VCOOFF_LP) | R/W | 0b |
| This bit controls the locking of the receive PLL. Setting this bit to 1 forces | NASR |
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| the receive PLL 10M to lock on the reference clock at all times. When in this |
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| mode, 10M data packets cannot be received. |
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| 0: Receive PLL 10M can lock on reference or line as needed (normal |
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| operation) |
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| 1: Receive PLL 10M locked onto reference clock at all times |
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9:5 | RESERVED | RO | - |
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4 | RO | 0b | |
| This bit shows the polarity state of the |
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| 0: Normal Polarity |
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| 1: Reversed Polarity |
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3:0 | RESERVED | RO | - |
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Note 14.61 Register bits designated as NASR are reset when the Port x PHY Reset is generated via the Reset Control Register (RESET_CTL). The NASR designation is only applicable when the Reset (PHY _ RST) bit of the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) is set.
Revision 1.4 | 302 | SMSC LAN9312 |
| DATASHEET |
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