SMSC LAN9312 15.5.8PIO Write Cycle Timing

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

15.5.8PIO Write Cycle Timing

Please refer to Section 8.4.8, "PIO Writes," on page 110 for a functional description of this mode.

A[x:2], END_SEL

		tcycle
			tah
tasu
	tcsl			tcsh

nCS, nWR

tdsutdh

D[31:0]

Figure 15.8 PIO Write Cycle Timing

Table 15.12 PIO Write Cycle Timing Values

SYMBOL	DESCRIPTION	MIN	TYP	MAX	UNITS
tcycle	Write Cycle Time	45			nS
tcsl	nCS, nWR Assertion Time	32			nS
tcsh	nCS, nWR De-assertion Time	13			nS
tasu	Address Setup to nCS, nWR Assertion	0			nS
tah	Address Hold Time	0			nS
tdsu	Data Setup to nCS, nWR De-assertion	7			nS
tdh	Data Hold Time	0			nS

Note: A PIO write cycle begins when both nCS and nWR are asserted. The cycle ends when either or both nCS and nWR are de-asserted. These signals may be asserted and de-asserted in any order.

Revision 1.4 (08-19-08)	450	SMSC LAN9312
	DATASHEET