High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

init

Idle

RX Interrupt

Read RX

Status

DWORD

Not Last Packet

Last Packet

Read RX

Packet

Figure 9.7 Host Receive Routine Using Interrupts

init

Read

RX_FIFO_INF

Valid Status DWORD

Read RX

Status

DWORD

Not Last Packet

Last Packet

Read RX

Packet

Figure 9.8 Host Receive Routine Using Polling

SMSC LAN9312

133

Revision 1.4 (08-19-08)

 

DATASHEET