SMSC LAN9312 9.9.3RX Status Format

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

read them as shown in Figure 9.9. It is assumed that the host has previously read the associated status word from the RX Status FIFO, to ascertain the data size and any error conditions.

Host Read	31	0
Order
1st	Optional offset DWORD0
2nd	.
	.
	Optional offset DWORDn
	ofs + First Data DWORD
	.
	.
	.
	.
	Last Data DWORD
	Optional Pad DWORD0
	.
	.
Last	Optional Pad DWORDn

Figure 9.9 RX Packet Format

9.9.3RX Status Format

	Note: Though the Host MAC is communicating locally with the switch fabric MAC, the events
	described in the RX Status word may still occur.
BITS	DESCRIPTION
31	Reserved. This bit is reserved. Reads 0.
30	Filtering Fail. When set, this bit indicates that the associated frame failed the address recognizing
	filtering.
29:16	Packet Length. The size, in bytes, of the corresponding received frame.
15	Error Status (ES). When set this bit indicates that the Host MAC Interface Layer (MIL) has reported
	an error. This bit is the Internal logical “or” of bits 11,7,6 and 1.
14	Reserved. These bits are reserved. Reads 0.
13	Broadcast Frame. When set, this bit indicates that the received frame has a Broadcast address.
12	Length Error (LE). When set, this bit indicates that the actual length does not match with the
	length/type field of the received frame.
11	Runt Frame. When set, this bit indicates that frame was prematurely terminated before the collision
	window (64 bytes). Runt frames are passed on to the host only if the Pass Bad Frames bit (PASSBAD)
	of the Host MAC Control Register (HMAC_CR) is set.
10	Multicast Frame. When set, this bit indicates that the received frame has a Multicast address.
9:8	Reserved. These bits are reserved. Reads 0.

SMSC LAN9312	135	Revision 1.4 (08-19-08)
	DATASHEET