High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
14.2.5.231588 Interrupt Status and Enable Register (1588_INT_STS_EN)Offset: | 198h | Size: | 32 bits |
This read/write register contains the IEEE 1588 interrupt status and enable bits.
Writing a 1 to any of the interrupt status bits acknowledges and clears the interrupt. If enabled, these interrupt bits are cascaded into bit 29 (1588_EVNT) of the Interrupt Status Register (INT_STS). Writing a 1 to any of the interrupt enable bits will enable the corresponding interrupt as a source. Status bits will still reflect the status of the interrupt source regardless of whether the source is enabled as an interrupt in this register. Bit 29 (1588_EVNT_EN) of the Interrupt Enable Register (INT_EN) must also be set in order for an actual system level interrupt to occur. Refer to Chapter 5, "System Interrupts," on page 49 for additional information.
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| DESCRIPTION | TYPE | DEFAULT |
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31:25 | RESERVED |
| RO | - | |
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24 | 1588 | Port 2 | RX Interrupt Enable (1588_PORT2_RX_EN) | R/W | 0b |
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23 | 1588 | Port 2 | TX Interrupt Enable (1588_PORT2_TX_EN) | R/W | 0b |
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22 | 1588 | Port 1 | RX Interrupt Enable (1588_PORT1_RX_EN) | R/W | 0b |
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21 | 1588 | Port 1 | TX Interrupt Enable (1588_PORT1_TX_EN) | R/W | 0b |
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20 | 1588 | Port 0(Host MAC) RX Interrupt Enable (1588_MII_RX_EN) | R/W | 0b | |
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19 | 1588 | Port 0(Host MAC) TX Interrupt Enable (1588_MII_TX_EN) | R/W | 0b | |
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18 | GPIO9 1588 Interrupt Enable (1588_GPIO9_EN) | R/W | 0b | ||
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17 | GPIO8 1588 Interrupt Enable (1588_GPIO8_EN) | R/W | 0b | ||
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16 | 1588 | Timer Interrupt Enable (1588_TIMER_EN) | R/W | 0b | |
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15:9 | RESERVED |
| RO | - | |
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8 | 1588 | Port 2 | RX Interrupt (1588_PORT2_RX_INT) | R/WC | 0b |
| This interrupt indicates that a packet received by Port 2 matches the |
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| configured PTP packet and the 1588 clock was captured. |
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7 | 1588 | Port 2 | TX Interrupt (1588_PORT2_TX_INT) | R/WC | 0b |
| This interrupt indicates that a packet transmitted by Port 2 matches the |
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| configured PTP packet and the 1588 clock was captured. |
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6 | 1588 | Port 1 | RX Interrupt (1588_PORT1_RX_INT) | R/WC | 0b |
| This interrupt indicates that a packet received by Port 1 matches the |
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| configured PTP packet and the 1588 clock was captured. |
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5 | 1588 | Port 1 | TX Interrupt (1588_PORT1_TX_INT) | R/WC | 0b |
| This interrupt indicates that a packet transmitted by Port 1 matches the |
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| configured PTP packet and the 1588 clock was captured. |
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4 | 1588 | Port 0(Host MAC) RX Interrupt (1588_MII_RX_INT) | R/WC | 0b | |
| This interrupt indicates that a packet from the switch fabric to the Host MAC |
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| the matches the configured PTP packet and the 1588 clock was captured. |
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| Note: | For Port 0, receive is defined as data from the switch fabric, while |
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| transmit is to the switch fabric. |
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Revision 1.4 | 226 | SMSC LAN9312 |
| DATASHEET |
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