High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
14.5.3.4Switch Engine ALR Read Data 0 Register (SWE_ALR_RD_DAT_0)Register #: | 1805h | Size: | 32 bits |
This register is used in conjunction with the Switch Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1) to read the ALR table. It contains the first 32 bits of the ALR entry and is loaded via the Get First Entry or Get Next Entry commands in the Switch Engine ALR Command Register (SWE_ALR_CMD). This register is only valid when either of the Valid or End of Table bits in the Switch Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1) are set.
BITS | DESCRIPTION | TYPE | DEFAULT |
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31:0 | MAC Address | RO | 00000000h |
| This field contains the first 32 bits of the ALR entry. These bits correspond |
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| to the first 32 bits of the MAC address. Bit 0 holds the LSB of the first byte |
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| (the multicast bit). |
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Revision 1.4 | 370 | SMSC LAN9312 |
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