SMSC LAN9312 15.5.4PIO Read Cycle Timing

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

15.5.4PIO Read Cycle Timing

Please refer to Section 8.4.4, "PIO Reads," on page 106 for a functional description of this mode.

A[x:2], END_SEL

		tcycle	tah
tasu
	tcsl			tcsh

nCS, nRD

							tdoff
				tcsdv	tdoh
	D[31:0]		tdon
		Figure 15.4 PIO Read Cycle Timing
		Table 15.8 PIO Read Cycle Timing Values
SYMBOL		DESCRIPTION			MIN	TYP		MAX	UNITS
tcycle	Read Cycle Time				45				nS
tcsl	nCS, nRD Assertion Time				32				nS
tcsh	nCS, nRD De-assertion Time				13				nS
tcsdv	nCS, nRD Valid to Data Valid							30	nS
tasu	Address setup to nCS, nRD Valid				0				nS
tah	Address Hold Time				0				nS
tdon	Data Buffer Turn On Time				0				nS
tdoff	Data Buffer Turn Off Time							9	nS
tdoh	Data Output Hold Time				0				nS

Note: A host PIO read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS and nRD are de-asserted. These signals may be asserted and de-asserted in any order.

Revision 1.4 (08-19-08)	446	SMSC LAN9312
	DATASHEET