High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
BITS |
| DESCRIPTION | TYPE |
| DEFAULT | |
|
|
|
|
|
|
|
3 | Flow Control on Multicast Frame (FCMULT) | R/W |
| 0b | ||
| When this bit is set, the Host MAC will assert back pressure when the AFC |
|
|
| ||
| level is reached and a multicast frame is received. This field has no function |
|
|
| ||
| in |
|
|
|
|
|
| 0: Flow Control on Multicast Frame Disabled |
|
|
| ||
| 1: Flow Control on Multicast Frame Enabled |
|
|
| ||
|
|
|
|
|
|
|
2 | Flow Control on Broadcast Frame (FCBRD) | R/W |
| 0b | ||
| When this bit is set, the Host MAC will assert back pressure when the AFC |
|
|
| ||
| level is reached and a broadcast frame is received. This field has no function |
|
|
| ||
| in |
|
|
|
|
|
| 0: Flow Control on Broadcast Frame Disabled |
|
|
| ||
| 1: Flow Control on Broadcast Frame Enabled |
|
|
| ||
|
|
|
|
|
|
|
1 | Flow Control on Address Decode (FCADD) | R/W |
| 0b | ||
| When this bit is set, the Host MAC will assert back pressure when the AFC |
|
|
| ||
| level is reached and a frame addressed to the Host MAC is received. This |
|
|
| ||
| field has no function in |
|
|
| ||
| 0: Flow Control on Address Decode Disabled |
|
|
| ||
| 1: Flow Control on Address Decode Enabled |
|
|
| ||
|
|
|
|
|
|
|
0 | Flow Control on Any Frame (FCANY) | R/W |
| 0b | ||
| When this bit is set, the Host MAC will assert back pressure, or transmit a |
|
|
| ||
| pause frame when the AFC level is reached and any frame is received. |
|
|
| ||
| Setting this bit enables |
|
|
| ||
| operating in |
|
|
| ||
| When this mode is enabled during |
|
|
| ||
| does not decode the Host MAC address and will send a JAM upon receipt |
|
|
| ||
| of a valid preamble (i.e., immediately at the beginning of the next frame after |
|
|
| ||
| the RX Data FIFO level is reached). |
|
|
| ||
| When this mode is enabled during |
|
|
| ||
| will immediately instruct the Host MAC to send a pause frame when the RX |
|
|
| ||
| Data FIFO level is reached. The MAC will queue the pause frame |
|
|
| ||
| transmission for the next available window. |
|
|
| ||
| Setting this bit overrides bits [3:1] of this register. |
|
|
| ||
|
|
|
|
|
|
|
|
| Table 14.2 Backpressure Duration Bit Mapping |
|
|
| |
|
|
|
|
| ||
|
| BACKPRESSURE DURATION |
| |||
|
|
|
|
|
| |
| [7:4] | 100Mbs Mode |
| 10Mbs Mode |
| |
|
|
|
|
|
| |
| 0h | 5uS |
| 7.2uS |
| |
|
|
|
|
|
| |
| 1h | 10uS |
| 12.2uS |
| |
|
|
|
|
|
| |
| 2h | 15uS |
| 17.2uS |
| |
|
|
|
|
|
| |
| 3h | 25uS |
| 27.2uS |
| |
|
|
|
|
|
| |
| 4h | 50uS |
| 52.2uS |
| |
|
|
|
|
|
| |
| 5h | 100uS |
| 102.2uS |
| |
|
|
|
|
|
| |
| 6h | 150uS |
| 152.2uS |
| |
|
|
|
|
|
| |
| 7h | 200uS |
| 202.2uS |
| |
|
|
|
|
|
|
|
Revision 1.4 | 190 | SMSC LAN9312 |
| DATASHEET |
|