High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

14.2.2.8Host MAC CSR Interface Data Register (MAC_CSR_DATA)

Offset:

0A8h

Size:

32 bits

This read-write register is used in conjunction with the Host MAC CSR Interface Command Register (MAC_CSR_CMD) to indirectly access the Host MAC CSR’s.

Note: The full list of Host MAC CSR’s are described in Section 14.3, "Host MAC Control and Status Registers," on page 269. For more information on the Host MAC, refer to Chapter 9, "Host MAC," on page 112.

BITS

 

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

31:0

Host MAC CSR Data

R/W

00000000h

 

This field contains the value read from or written to the Host MAC CSR as

 

 

 

specified in the Host MAC CSR Interface Command Register

 

 

 

(MAC_CSR_CMD). Upon a read, the value returned depends on the R/nW

 

 

 

bit in the MAC_CSR_CMD register. If R/nW is a 1, the data in this register

 

 

 

is from the Host MAC. If R/nW is 0, the data is the value that was last written

 

 

 

into this register.

 

 

 

Note:

The MAC_CSR_CMD and MAC_CSR_DATA registers must not be

 

 

 

 

modified until the CSR Busy bit is cleared in the MAC_CSR_CMD

 

 

 

 

register.

 

 

 

 

 

 

 

Revision 1.4 (08-19-08)

188

SMSC LAN9312

 

DATASHEET