High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
7.2.2.3NRZI and MLT-3 DecodingThe DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then converted to an NRZI data stream.
7.2.2.4Descrambler and SIPOThe descrambler performs an inverse function to the scrambler in the transmitter and also performs the Serial In Parallel Out (SIPO) conversion of the data.
During reception of IDLE (/I/) symbols. the descrambler synchronizes its descrambler key to the incoming stream. Once synchronization is achieved, the descrambler locks on this key and is able to descramble incoming data.
Special logic in the descrambler ensures synchronization with the remote PHY by searching for IDLE symbols within a window of 4000 bytes (40us). This window ensures that a maximum packet size of 1514 bytes, allowed by the IEEE 802.3 standard, can be received with no interference. If no IDLE- symbols are detected within this time-period, receive operation is aborted and the descrambler re-starts the synchronization process.
The de-scrambled signal is then aligned into 5-bit code-groups by recognizing the /J/K/ Start-of-Stream Delimiter (SSD) pair at the start of a packet. Once the code-word alignment is determined, it is stored and utilized until the next start of frame.
7.2.2.55B/4B DecodingThe 5-bit code-groups are translated into 4-bit data nibbles according to the 4B/5B table shown in Table 7.2. The translated data is presented on the internal MII RXD[3:0] signal lines to the switch fabric MAC. The SSD, /J/K/, is translated to “0101 0101” as the first 2 nibbles of the MAC preamble. Reception of the SSD causes the PHY to assert the RXDV signal, indicating that valid data is available on the RXD bus. Successive valid code-groups are translated to data nibbles. Reception of either the End of Stream Delimiter (ESD) consisting of the /T/R/ symbols, or at least two /I/ symbols causes the PHY to de-assert carrier sense and RXDV. These symbols are not translated into data.
7.2.2.6Receiver ErrorsDuring a frame, unexpected code-groups are considered receive errors. Expected code groups are the DATA set (0 through F), and the /T/R/ (ESD) symbol pair. When a receive error occurs, the internal MII’s RXER signal is asserted and arbitrary data is driven onto the internal receive data bus (RXD) to the switch fabric MAC. Should an error be detected during the time that the /J/K/ delimiter is being decoded (bad SSD error), RXER is asserted and the value 1110b is driven onto the internal receive data bus (RXD) to the switch fabric MAC. Note that the internal MII’s data valid signal (RXDV) is not yet asserted when the bad SSD occurs.
7.2.2.7MII MAC InterfaceFor reception, the 4-bit data nibbles are sent to the MII MAC Interface block where they are sent via MII to the switch fabric MAC. The MII MAC Interface is described in detail in Section 7.2.7, "MII MAC Interface".
Note: The PHY is connected to the switch fabric MAC via standard MII signals. Refer to the IEEE
802.3specification for additional details.
