High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

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11.4IEEE 1588 Clock/Events

The IEEE 1588 Clock/Events block is responsible for generating and controlling all IEEE 1588 clock related events. A 64-bit comparator is included in this block which compares the 64-bit IEEE 1588 clock with a 64-bit Clock Target loaded in the 1588 Clock Target High-DWORD Register (1588 _ CLOCK _ TARGET _ HI) and 1588 Clock Target Low - DWORD Register (1588_CLOCK_TARGET_LO).

When the IEEE 1588 clock equals the Clock Target, a clock event occurs which triggers the following:

„The maskable interrupt 1588_TIMER_INT is set in the 1588 Interrupt Status and Enable Register (1588_INT_STS_EN).

„The RELOAD_ADD bit in the 1588 Configuration Register (1588_CONFIG) is checked to determine the new Clock Target behavior:

–RELOAD_ADD = 1:

The new Clock Target is loaded from the 64-bit Reload / Add Registers (1588 Clock Target Reload High-DWORD Register (1588_CLOCK_TARGET_RELOAD_HI) and 1588 Clock Target Reload/Add Low-DWORD Register (1588_CLOCK_TARGET_RELOAD_LO)).

–RELOAD_ADD = 0:

The Clock Target is incremented by the 1588 Clock Target Reload/Add Low-DWORD Register (1588_CLOCK_TARGET_RELOAD_LO).

Note: Writing the IEEE 1588 clock may cause the interrupt event to occur if the new IEEE 1588 clock value is set equal to the current Clock Target.

The Clock Target reload function (RELOAD_ADD = 1) allows the host to pre-load the next trigger time. The add function (RELOAD_ADD = 0), allows for a repeatable event. When the Clock Target overflows, it will wrap around past 0, as will the 64-bit IEEE 1588 clock. Since the Clock Target and Reload / Add Registers are 64-bits, they require two 32-bit write cycles, one to each half, before the registers are affected. The writes may be in any order.

11.5IEEE 1588 GPIOs

In addition to time stamping PTP packets, the IEEE 1588 clock value can be saved into a set of clock capture registers based on the GPIO[9:8] inputs. When configured as outputs, GPIO[9:8] can be used to output a signal based on an IEEE 1588 clock target compare event. Refer to Section 13.2.1, "GPIO IEEE 1588 Timestamping," on page 163 for information on using GPIO[9:8] for IEEE 1588 time stamping functions.

11.6IEEE 1588 Interrupts

The IEEE 1588 hardware time stamp unit provides multiple interrupt conditions. These include time stamp indication on the transmitter and receiver side of each port, individual GPIO[9:8] input time stamp interrupts, and a clock comparison event interrupt. All IEEE 1588 interrupts are located in the 1588 Interrupt Status and Enable Register (1588_INT_STS_EN) and are fully maskable via their respective enable bits. Refer to Section 14.2.5.23, "1588 Interrupt Status and Enable Register (1588_INT_STS_EN)," on page 226 for bit-level definitions of all IEEE 1588 interrupts and enables.

All IEEE 1588 interrupts are ANDed with their individual enables and then ORed, as shown in Figure 11.1, generating the 1588_EVNT bit of the Interrupt Status Register (INT_STS).

When configured as an input, GPIO[9:8] have the added functionality of clearing the Clock Target interrupt bit (1588_TIMER_INT) of the 1588 Interrupt Status and Enable Register (1588_INT_STS_EN) on an active edge. GPIO inputs must be active for greater than 40 nS to be recognized as clear events. For more information on IEEE 1588 GPIO interrupts, refer to Section 13.2.2, "GPIO Interrupts," on page 163.

Refer to Chapter 5, "System Interrupts," on page 49 for additional information on the LAN9312 interrupts.

Revision 1.4 (08-19-08)

160

SMSC LAN9312

 

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