High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

14.2.5.151588 Clock Addend Register (1588_CLOCK_ADDEND)

Offset:

178h

Size:

32 bits

This read/write register is responsible for adjusting the 64-bit 1588 Clock frequency. Refer to Chapter 11, "IEEE 1588 Hardware Time Stamp Unit," on page 154 for details on how to properly use this register.

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

31:0

Clock Addend (CLOCK_ADDEND)

R/W

00000000h

 

This 32-bit value is added to the 1588 frequency divisor accumulator every

 

 

 

cycle. This allows the base 100MHz frequency of the 64-bit 1588 Clock to

 

 

 

be adjusted accordingly.

 

 

 

 

 

 

SMSC LAN9312

215

Revision 1.4 (08-19-08)

 

DATASHEET