High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

10.2.4.2EEPROM Valid Flag

Following the release of nRST, POR, DIGITAL_RST, or a RELOAD command, the EEPROM Loader starts by reading the first byte of data from the EEPROM. If the value of A5h is not read from the first byte, the EEPROM Loader will load the current configuration strap values into the PHY registers (see Section 10.2.4.4.1) and then terminate, clearing the EPC_BUSY bit in the EEPROM Command Register (E2P_CMD). Otherwise, the EEPROM Loader will continue reading sequential bytes from the

EEPROM.

10.2.4.3MAC Address

The next six bytes in the EEPROM, after the EEPROM Valid Flag, are written into the Host MAC Address High Register (HMAC_ADDRH) and Host MAC Address Low Register (HMAC_ADDRL), and the Switch Fabric MAC Address High Register (SWITCH_MAC_ADDRH) and Switch Fabric MAC Address Low Register (SWITCH_MAC_ADDRL). The EEPROM bytes are written into the MAC address registers in the order specified in Table 10.7. Refer to Section 9.6, "Host MAC Address," on page 119 for additional information on MAC address loading.

10.2.4.3.1HOST MAC ADDRESS RELOAD

While the EEPROM Loader is in the wait state, if a Host MAC reset is detected (via the Soft Reset bit in the Hardware Configuration Register (HW_CFG)), the EEPROM Loader will read byte 0. If the byte 0 value is A5h, the EEPROM Loader will read bytes 1 through 6 from the EEPROM and reload the Host MAC Address High Register (HMAC_ADDRH) and Host MAC Address Low Register (HMAC_ADDRL). During this time, the EPC_BUSY bit in the EEPROM Command Register (E2P_CMD) is set.

Note: The switch MAC address registers are not reloaded due to this condition.

10.2.4.4Soft-Straps

The 7th byte of data to be read from the EEPROM is the Configuration Strap Values Valid Flag. If this byte has a value of A5h, the next 4 bytes of data (8-11) are written into the configuration strap registers per the assignments detailed in Table 10.8. If the flag byte is not A5h, these next 4 bytes are skipped (they are still read to maintain the data burst, but are discarded). However, the current configuration strap values are still loaded into the PHY registers (see Section 10.2.4.4.1). Refer to Section 4.2.4, "Configuration Straps," on page 40 for more information on the LAN9312 configuration straps.

Table 10.8 EEPROM Configuration Bits

BYTE/BIT

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

Byte 8

BP_EN_

FD_FC_

manual_

manual_mdix

auto_mdix_

speed_

duplex_

autoneg_

 

strap_1

strap_1

FC_strap_1

_strap_1

strap_1

strap_1

strap_1

strap_1

 

 

 

 

 

 

 

 

 

Byte 9

BP_EN_

FD_FC_

manual_

manual_mdix

auto_mdix_

speed_

duplex_

autoneg_

 

strap_2

strap_2

FC_strap_2

_strap_2

strap_2

strap_2

strap_2

strap_2

 

 

 

 

 

 

 

 

 

Byte 10

LED_fun_strap[1:0]

BP_EN_

FD_FC_

manual_FC

speed_

duplex_pol_

SQE_test_

 

 

 

strap_mii

strap_mii

_strap_mii

strap_mii

strap_mii

disable_strap

 

 

 

 

 

 

 

 

_mii

 

 

 

 

 

 

 

 

 

Byte 11

 

 

 

LED_en_strap[7:0]

 

 

 

 

 

 

 

 

 

 

 

 

10.2.4.4.1PHY REGISTERS SYNCHRONIZATION

Some PHY register defaults are based on configuration straps. In order to maintain consistency between the updated configuration strap registers and the PHY registers, the Port x PHY Auto- Negotiation Advertisement Register (PHY_AN_ADV_x), Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x), and Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) are written when the EEPROM Loader is run.

SMSC LAN9312

151

Revision 1.4 (08-19-08)

 

DATASHEET