High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
Software (general purpose)
A dedicated programmable IRQ interrupt output pin is provided for external indication of any LAN9312 interrupts. The IRQ pin is controlled via the Interrupt Configuration Register (IRQ_CFG), which allows configuration of the IRQ buffer type, polarity, and
2.2.3Switch Fabric
The Switch Fabric consists of the following major function blocks:
10/100 MACs
There is one 10/100 Ethernet MAC per switch fabric port, which provides basic 10/100 Ethernet functionality, including transmission deferral, collision
Switch Engine
This block, consisting of a 3 port VLAN layer 2 switching engine, provides the control for all forwarding/filtering rules and supports untagged, VLAN tagged, and priority tagged frames. The switch engine provides an extensive feature set which includes spanning tree protocol support, multicast packet filtering and Quality of Service (QoS) packet prioritization by VLAN tag, destination address, and port default value or DIFFSERV/TOS, allowing for a range of prioritization implementations. A 1K entry forwarding table provides ample room for MAC address forwarding tables.
Buffer Manager
This block controls the free buffer space,
Switch CSRs
This block contains all switch related control and status registers, and allows all aspects of the switch fabric to be managed. These registers are indirectly accessible via the memory mapped system control and status registers
2.2.4Ethernet PHYs
The LAN9312 contains three PHYs: Port 1 PHY, Port 2 PHY and a Virtual PHY. The Port 1 & 2 PHYs are identical in functionality and each connect their corresponding Ethernet signal pins to the switch fabric MAC of their respective port. These PHYs interface with their respective MAC via an internal MII interface. The Virtual PHY provides the virtual functionality of a PHY and allows connection of the Host MAC to port 0 of the switch fabric as if it was connected to a single port PHY. All PHYs comply with the IEEE 802.3 Physical Layer for Twisted Pair Ethernet and can be configured for full/half duplex 100 Mbps
802.3 (clause 22.2.4) specified MII management register set.
2.2.5Host Bus Interface (HBI)
The Host Bus Interface (HBI) module provides a
Asynchronous
-Host Data Bus Endianess Control
-Direct FIFO Access Modes
SMSC LAN9312 | 23 | Revision 1.4 |
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