High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
The Filter i Offset register defines the offset in the frame’s destination address field from which the frames are examined by Filter i. Table 9.5 describes the Filter i Offset bit fields.
Table 9.5 Filter i Offset Bit Definitions
FILTER i OFFSET DESCRIPTION
FIELD DESCRIPTION
7:0 Pattern Offset: The offset of the first byte in the frame on which CRC is checked for
The Filter i
Table 9.6 describes the Filter i
Table 9.6 Filter i
FILTER i
FIELD DESCRIPTION
15:0 Pattern
9.5.1Magic Packet Detection
Setting the Magic Packet Enable bit (MPEN) in the Host MAC
In Magic Packet mode, the Host MAC constantly monitors each frame addressed to the node for a specific Magic Packet pattern. Only packets matching the Host MAC address or broadcast address are checked for the Magic Packet requirements. Once the address requirement has been met, the Host MAC checks the received frame for the pattern 48’hFF_FF_FF_FF_FF_FF after the destination and source address field. The Host MAC then looks in the frame for 16 repetitions of the Host MAC address without any breaks or interruptions. In case of a break in the 16 address repetitions, the Host MAC again scans for the 48'hFF_FF_FF_FF_FF_FF pattern in the incoming frame. The 16 repetitions may be anywhere in the frame but must be preceded by the synchronization stream. The device will also accept a multicast frame, as long as it detects the 16 duplications of the Host MAC address.
For example, if the Host MAC address is 00h 11h 22h 33h 44h 55h, then the MAC scans for the following data sequence in an Ethernet frame:
Revision 1.4 | 118 | SMSC LAN9312 |
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