High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

Table 3.3 LAN Port 1 & 2 Power and Common Pins (continued)

 

 

 

BUFFER

 

PIN

NAME

SYMBOL

TYPE

DESCRIPTION

 

 

 

 

 

 

+3.3V Port 2

VDD33A2

P

+3.3V Port 2 Analog Power Supply

122,125

Analog Power

 

 

Refer to the LAN9312 application note for

Supply

 

 

 

 

 

 

additional connection information.

 

 

 

 

 

 

+3.3V Master

VDD33BIAS

P

+3.3V Master Bias Power Supply

120

Bias Power

 

 

Refer to the LAN9312 application note for

Supply

 

 

 

 

 

 

additional connection information.

 

 

 

 

 

 

Port 2

VDD18TX2

P

Port 2 Transmitter +1.8V Power Supply: This pin

 

Transmitter

 

 

is supplied from the internal PHY voltage regulator.

 

+1.8V Power

 

 

This pin must be tied to the VDD18TX1 pin for

121

Supply

 

 

proper operation.

 

 

 

 

 

 

 

Refer to the LAN9312 application note for

 

 

 

 

additional connection information.

 

 

 

 

 

 

Port 1

VDD18TX1

P

+1.8V Port 1 Transmitter Power Supply: This pin

 

Transmitter

 

 

must be connected directly to the VDD18TX2 pin

118

+1.8V Power

 

 

for proper operation.

 

Supply

 

 

Refer to the LAN9312 application note for

 

 

 

 

 

 

 

 

additional connection information.

 

 

 

 

 

 

 

Table 3.4 Host Bus Interface Pins

 

 

 

 

 

 

 

 

BUFFER

 

PIN

NAME

SYMBOL

TYPE

DESCRIPTION

 

 

 

 

 

4-6,

Host Bus

D[31:0]

IS/O8

Host Bus Data High: Bits 31-0 of the Host Bus 32-

8-12,

Data

 

 

bit data port.

15-17,19,

 

 

 

Note: Big and little endianess is supported.

20,22-26,

 

 

 

 

 

 

 

28-32,

 

 

 

 

34-38,

 

 

 

 

41-44

 

 

 

 

 

 

 

 

 

 

Host Bus

A[9:2]

IS

Host Bus Address: 9-bit Host Bus Address Port

45,47,

Address

 

 

used to select Internal CSR’s and TX and RX

49-53,

 

 

 

FIFO’s.

 

 

 

 

55

 

 

 

Note: The A0 and A1 bits are not used because

 

 

 

 

the LAN9312 must be accessed on

 

 

 

 

DWORD boundaries.

 

 

 

 

 

57

Read Strobe

nRD

IS

Read Strobe: Active low strobe to indicate a read

 

 

 

cycle. This signal is qualified by the nCS chip

 

 

 

 

select.

 

 

 

 

 

58

Write Strobe

nWR

IS

Write Strobe: Active low strobe to indicate a write

 

 

 

cycle. This signal is qualified by the nCS chip

 

 

 

 

select.

 

 

 

 

 

59

Chip Select

nCS

IS

Chip Select: Active low signal used to qualify read

 

 

 

and write operations.

 

 

 

 

 

 

 

 

 

Revision 1.4 (08-19-08)

30

SMSC LAN9312

 

DATASHEET