High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Note: The power-down modes of each PHY (Port 1 PHY and Port 2 PHY) are controlled independently.
Note: The PHY power-down modes do not reload or reset the PHY registers.
7.2.9.1PHY General Power-Down
This power-down mode is controlled by bit 11 of the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x). In this mode the entire PHY, except the PHY management control interface, is powered down. The PHY will remain in this power-down state as long as bit 11 is set. When bit 11 is cleared, the PHY powers up and is automatically reset.
7.2.9.2PHY Energy Detect Power-Down
This power-down mode is enabled by setting bit 13 (EDPWRDOWN) of the Port x PHY Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x). When in this mode, if no energy is detected on the line, the entire PHY is powered down except for the PHY management control interface, the SQUELCH circuit, and the ENERGYON logic. The ENERGYON logic is used to detect the presence of valid energy from 100BASE-TX, 10BASE-T, or auto-negotiation signals and is responsible for driving the ENERGYON signal (bit 1) of the Port x PHY Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x).
In this mode, when the ENERGYON signal is cleared, the PHY is powered down and no data is transmitted from the PHY. When energy is received, via link pulses or packets, the ENERGYON signal goes high, and the PHY powers up. The PHY automatically resets itself into its previous state prior to power-down, and asserts the INT7 interrupt (bit 7) of the Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x). The first and possibly second packet to activate ENERGYON may be lost.
When bit 13 (EDPWRDOWN) of the Port x PHY Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x) is low, energy detect power-down is disabled.
The energy detect power down feature is part of the broader power management features of the LAN9312 and can be used to trigger the power management event output pin (PME). This is accomplished by enabling the energy detect power-down feature of the PHY as described above, and setting the corresponding energy detect enable (bit 14 for Port 1 PHY, bit 15 for Port 2 PHY) of the Power Management Control Register (PMT_CTRL). Refer to Section 4.3, "Power Management," on page 46 for additional information.
7.2.10PHY Resets
In addition to the chip-level hardware reset (nRST) and Power-On Reset (POR), the PHY supports three block specific resets. These are discussed in the following sections. For detailed information on all LAN9312 resets and the reset sequence refer to Section 4.2, "Resets," on page 36.
Note: The DIGITAL_RST bit in the Reset Control Register (RESET_CTL) does not reset the PHYs. Only a hardware reset (nRST) or an EEPROM RELOAD command will automatically reload the configuration strap values into the PHY registers. For all other PHY resets, these values will need to be manually configured via software.
7.2.10.1PHY Software Reset via RESET_CTL
The PHY can be reset via the Reset Control Register (RESET_CTL). The Port 1 PHY is reset by setting bit 1 (PHY1_RST), and the Port 2 PHY is reset by setting bit 2 (PHY2_RST). These bits are self clearing after approximately 102uS. This reset does not reload the configuration strap values into the PHY registers.
