High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
BITS | DESCRIPTION | TYPE | DEFAULT |
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23 | Master/Slave Port 1 (M_nS_1) | R/W | 0b |
| When set, Port 1 is a time clock master and captures timestamps when a |
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| Sync packet is transmitted and when a Delay_Req is received. When |
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| cleared, Port 1 is a time clock slave and captures timestamps when a |
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| Delay_Req packet is transmitted and when a Sync packet is received. |
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22 | Primary MAC Address Enable Port 1 (MAC_PRI_EN_1) | R/W | 1b |
| This bit enables/disables the primary MAC address on Port 1. |
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| 0: Disables primary MAC address on Port 1 |
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| 1: Enables MAC address 01:00:5E:00:01:81 as a PTP address on Port 1 |
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21 | Alternate MAC Address 1 Enable Port 1 (MAC_ALT1_EN_1) | R/W | 0b |
| This bit enables/disables the alternate MAC address 1 on Port 1. |
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| 0: Disables alternate MAC address on Port 1 |
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| 1: Enables MAC address 01:00:5E:00:01:82 as a PTP address on Port 1 |
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20 | Alternate MAC Address 2 Enable Port 1 (MAC_ALT2_EN_1) | R/W | 0b |
| This bit enables/disables the alternate MAC address 2 on Port 1. |
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| 0: Disables alternate MAC address on Port 1 |
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| 1: Enables MAC address 01:00:5E:00:01:83 as a PTP address on Port 1 |
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19 | Alternate MAC Address 3 Enable Port 1 (MAC_ALT3_EN_1) | R/W | 0b |
| This bit enables/disables the alternate MAC address 3 on Port 1. |
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| 0: Disables alternate MAC address on Port 1 |
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| 1: Enables MAC address 01:00:5E:00:01:84 as a PTP address on Port 1 |
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18 | User Defined MAC Address Enable Port 1 (MAC_USER_EN_1) | R/W | 0b |
| This bit enables/disables the auxiliary MAC address on Port 1. The auxiliary |
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| address is defined via the 1588_AUX_MAC_HI and 1588_AUX_MAC_LO |
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| registers. |
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| 0: Disables auxiliary MAC address on Port 1 |
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| 1: Enables auxiliary MAC address as a PTP address on Port 1 |
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17 | Lock Enable RX Port 1 (LOCK_RX_1) | R/W | 1b |
| This bit enables/disables the RX lock. This lock prevents a 1588 capture |
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| from overwriting the Clock, UUDI and Sequence ID values if the 1588 RX |
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| interrupt for Port 1 is ready set due to a previous capture. |
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| 0: Disables RX Port 1 Lock |
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| 1: Enables RX Port 1 Lock |
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16 | Lock Enable TX Port 1 (LOCK_TX_1) | R/W | 1b |
| This bit enables/disables the TX lock. This lock prevents a 1588 capture |
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| from overwriting the Clock, UUDI and Sequence ID values if the 1588 TX |
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| interrupt for Port 1 is ready set due to a previous capture. |
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| 0: Disables TX Port 1 Lock |
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| 1: Enables TX Port 1 Lock |
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15 | Master/Slave Port 0(Host MAC)(M_nS_MII) | R/W | 0b |
| When set, Port 0 is a time clock master and captures timestamps when a |
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| Sync packet is transmitted and when a Delay_Req is received. When |
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| cleared, Port 0 is a time clock slave and captures timestamps when a |
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| Delay_Req packet is transmitted and when a Sync packet is received. |
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| Note: For Port 0, receive is defined as data from the switch fabric, while |
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| transmit is defined as data to the switch fabric. |
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14 | Primary MAC Address Enable Port 0(Host MAC) (MAC_PRI_EN_MII) | R/W | 1b |
| This bit enables/disables the primary MAC address on Port 0. |
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| 0: Disables primary MAC address on Port 0 |
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| 1: Enables MAC address 01:00:5E:00:01:81 as a PTP address on Port 0 |
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SMSC LAN9312 | 223 | Revision 1.4 |
| DATASHEET |
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