High Performance Two Port 10/100 Managed Ethernet Switch with
Datasheet
BITS | DESCRIPTION | TYPE | DEFAULT |
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0 | Flow Control Busy (FCBSY) | R/W | 0b |
| In |
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| MAC Flow Control (HMAC_FLOW) register. To initiate a PAUSE control |
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| frame, the bit must be set. During a transfer of control frame, this bit |
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| continues to be set, signifying that a frame transmission is in progress. After |
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| the PAUSE control frame’s transmission is complete, the Host MAC resets |
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| the bit to 0. |
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| Backpressure Enable (BkPresEn) |
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| In |
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| set high whenever backpressure is transmitted. |
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| Notes: |
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| When writing this register, the FCBSY bit must always be zero. |
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| Applications must always write a zero to this bit |
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Revision 1.4 | 280 | SMSC LAN9312 |
| DATASHEET |
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