High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

0

Flow Control Busy (FCBSY)

R/W

0b

 

In full-duplex mode, this bit should read logical 0 before writing to the Host

 

 

 

MAC Flow Control (HMAC_FLOW) register. To initiate a PAUSE control

 

 

 

frame, the bit must be set. During a transfer of control frame, this bit

 

 

 

continues to be set, signifying that a frame transmission is in progress. After

 

 

 

the PAUSE control frame’s transmission is complete, the Host MAC resets

 

 

 

the bit to 0.

 

 

 

Backpressure Enable (BkPresEn)

 

 

 

In half-duplex mode, this signal functions as a backpressure enable and is

 

 

 

set high whenever backpressure is transmitted.

 

 

 

Notes:

 

 

 

„ When writing this register, the FCBSY bit must always be zero.

 

 

 

„ Applications must always write a zero to this bit

 

 

 

 

 

 

Revision 1.4 (08-19-08)

280

SMSC LAN9312

 

DATASHEET