SMSC LAN9312 15.4DC Specifications

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

15.4DC Specifications

Table 15.3 I/O Buffer Characteristics

PARAMETER	SYMBOL	MIN	TYP	MAX	UNITS	NOTES
IS Type Input Buffer
Low Input Level	VILI	-0.3			V
High Input Level	VIHI			3.6	V
Negative-Going Threshold	VILT	1.01	1.18	1.35	V	Schmitt trigger
Positive-Going Threshold	VIHT	1.39	1.6	1.8	V	Schmitt trigger
SchmittTrigger Hysteresis	VHYS	345	420	485	mV
(VIHT - VILT)
Input Leakage	IIN	-10		10	uA	Note 15.5
Input Capacitance	CIN			3	pF
O8 Type Buffers
Low Output Level	VOL			0.4	V	IOL = 8mA
High Output Level	VOH	VDD33IO - 0.4			V	IOH = -8mA
OD8 Type Buffer
Low Output Level	VOL			0.4	V	IOL = 8mA
O12 Type Buffer
Low Output Level	VOL			0.4	V	IOL = 12mA
High Output Level	VOH	VDD33IO - 0.4			V	IOH = -12mA
OD12 Type Buffer
Low Output Level	VOL			0.4	V	IOL = 12mA
ICLK Type Buffer (XI Input)						Note 15.6
Low Input Level	VILI	-0.3		0.5	V
High Input Level	VIHI	1.4		3.6	V

Note 15.5 This specification applies to all IS type inputs and tri-stated bi-directional pins. Internal pull- down and pull-up resistors add +/- 50uA per-pin (typical).

Note 15.6 XI can optionally be driven from a 25MHz single-ended clock oscillator.

Table 15.4 100BASE-TX Transceiver Characteristics

PARAMETER	SYMBOL	MIN	TYP	MAX	UNITS	NOTES
Peak Differential Output Voltage High	VPPH	950	-	1050	mVpk	Note 15.7
Peak Differential Output Voltage Low	VPPL	-950	-	-1050	mVpk	Note 15.7
Signal Amplitude Symmetry	VSS	98	-	102	%	Note 15.7
Signal Rise and Fall Time	TRF	3.0	-	5.0	nS	Note 15.7
Rise and Fall Symmetry	TRFS	-	-	0.5	nS	Note 15.7
Duty Cycle Distortion	DCD	35	50	65	%	Note 15.8

Revision 1.4 (08-19-08)	442	SMSC LAN9312
	DATASHEET