SMSC LAN9312 14.2.2.2Transmit Configuration Register (TX_CFG)

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

14.2.2.2Transmit Configuration Register (TX_CFG)

Offset: 070h Size: 32 bits

This register controls the Host MAC transmit functions.

BITS	DESCRIPTION	TYPE	DEFAULT
31:16	RESERVED	RO	-
15	Force TX Status Discard (TXS_DUMP)	WO	0b
	When a 1 is written to this bit, the TX Status FIFO is cleared of all pending	SC
	status DWORD’s and the TX status pointers are cleared to zero.
14	Force TX Data Discard (TXD_DUMP)	WO	0b
	When a 1 is written to this bit, the TX Data FIFO is cleared of all pending	SC
	data and the TX data pointers are cleared to zero.
13:3	RESERVED	RO	-
2	TX Status Allow Overrun (TXSAO)	R/W	0b
	When this bit is cleared, Host MAC data transmission is suspended if the
	TX Status FIFO becomes full. Setting this bit high allows the transmitter to
	continue operation with a full TX Status FIFO.
	Note: This bit does not affect the operation of the TX Status FIFO Full
	Interrupt (TSFF).
1	Transmitter Enable (TX_ON)	R/W	0b
	When this bit is set, the Host MAC transmitter is enabled. Any data in the
	TX Data FIFO will be sent. This bit is cleared automatically when the
	STOP_TX bit is set and the transmitter is halted.
0	Stop Transmitter (STOP_TX)	R/W	0b
	When this bit is set, the Host MAC transmitter will finish the current frame,	SC
	and will then stop transmitting. When the transmitter has stopped this bit will
	clear. All writes to this bit are ignored while this bit is high.

Revision 1.4 (08-19-08)	182	SMSC LAN9312
	DATASHEET